// $ANTLR 3.3 Nov 30, 2010 12:45:30 C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g 2011-02-16 15:51:14
package org.clothocad.tool.cello;
import org.antlr.runtime.*;
import java.util.Stack;
import java.util.List;
import java.util.ArrayList;
import java.util.Map;
import java.util.HashMap;
public class VerilogLexer extends Lexer {
public static final int EOF=-1;
public static final int T__67=67;
public static final int T__68=68;
public static final int T__69=69;
public static final int T__70=70;
public static final int T__71=71;
public static final int T__72=72;
public static final int T__73=73;
public static final int T__74=74;
public static final int T__75=75;
public static final int T__76=76;
public static final int T__77=77;
public static final int T__78=78;
public static final int T__79=79;
public static final int T__80=80;
public static final int T__81=81;
public static final int T__82=82;
public static final int T__83=83;
public static final int T__84=84;
public static final int T__85=85;
public static final int T__86=86;
public static final int T__87=87;
public static final int T__88=88;
public static final int T__89=89;
public static final int T__90=90;
public static final int T__91=91;
public static final int T__92=92;
public static final int T__93=93;
public static final int T__94=94;
public static final int T__95=95;
public static final int T__96=96;
public static final int T__97=97;
public static final int T__98=98;
public static final int T__99=99;
public static final int T__100=100;
public static final int T__101=101;
public static final int T__102=102;
public static final int T__103=103;
public static final int T__104=104;
public static final int T__105=105;
public static final int T__106=106;
public static final int T__107=107;
public static final int T__108=108;
public static final int T__109=109;
public static final int T__110=110;
public static final int T__111=111;
public static final int T__112=112;
public static final int T__113=113;
public static final int T__114=114;
public static final int T__115=115;
public static final int T__116=116;
public static final int T__117=117;
public static final int T__118=118;
public static final int T__119=119;
public static final int T__120=120;
public static final int T__121=121;
public static final int T__122=122;
public static final int T__123=123;
public static final int T__124=124;
public static final int T__125=125;
public static final int T__126=126;
public static final int T__127=127;
public static final int T__128=128;
public static final int T__129=129;
public static final int T__130=130;
public static final int T__131=131;
public static final int T__132=132;
public static final int T__133=133;
public static final int T__134=134;
public static final int T__135=135;
public static final int T__136=136;
public static final int T__137=137;
public static final int T__138=138;
public static final int T__139=139;
public static final int T__140=140;
public static final int T__141=141;
public static final int T__142=142;
public static final int T__143=143;
public static final int T__144=144;
public static final int T__145=145;
public static final int T__146=146;
public static final int T__147=147;
public static final int T__148=148;
public static final int T__149=149;
public static final int T__150=150;
public static final int T__151=151;
public static final int T__152=152;
public static final int T__153=153;
public static final int T__154=154;
public static final int T__155=155;
public static final int T__156=156;
public static final int T__157=157;
public static final int T__158=158;
public static final int T__159=159;
public static final int T__160=160;
public static final int T__161=161;
public static final int T__162=162;
public static final int T__163=163;
public static final int T__164=164;
public static final int T__165=165;
public static final int T__166=166;
public static final int T__167=167;
public static final int T__168=168;
public static final int T__169=169;
public static final int T__170=170;
public static final int T__171=171;
public static final int T__172=172;
public static final int T__173=173;
public static final int T__174=174;
public static final int T__175=175;
public static final int T__176=176;
public static final int T__177=177;
public static final int T__178=178;
public static final int T__179=179;
public static final int SEMI=4;
public static final int LPAREN=5;
public static final int COMMA=6;
public static final int RPAREN=7;
public static final int DOT=8;
public static final int LCURLY=9;
public static final int RCURLY=10;
public static final int LBRACK=11;
public static final int COLON=12;
public static final int RBRACK=13;
public static final int ASSIGN=14;
public static final int NUMBER=15;
public static final int KW_TRIREG=16;
public static final int KW_ASSIGN=17;
public static final int POUND=18;
public static final int IDENTIFIER=19;
public static final int LE=20;
public static final int TRIGGER=21;
public static final int SYSTEM_TASK_NAME=22;
public static final int PPATH=23;
public static final int FPATH=24;
public static final int PLUS=25;
public static final int MINUS=26;
public static final int STRING=27;
public static final int DEFINE=28;
public static final int QUESTION=29;
public static final int LNOT=30;
public static final int BNOT=31;
public static final int BAND=32;
public static final int RNAND=33;
public static final int BOR=34;
public static final int RNOR=35;
public static final int BXOR=36;
public static final int BXNOR=37;
public static final int STAR=38;
public static final int DIV=39;
public static final int MOD=40;
public static final int EQUAL=41;
public static final int NOT_EQ=42;
public static final int EQ_CASE=43;
public static final int NOT_EQ_CASE=44;
public static final int LAND=45;
public static final int LOR=46;
public static final int LT_=47;
public static final int GT=48;
public static final int GE=49;
public static final int SR=50;
public static final int SL=51;
public static final int ESCAPED_IDENTIFIER=52;
public static final int AT=53;
public static final int VOCAB=54;
public static final int SIZE=55;
public static final int BASE=56;
public static final int SIZED_DIGIT=57;
public static final int SIZED_NUMBER=58;
public static final int UNSIZED_NUMBER=59;
public static final int DIGIT=60;
public static final int HEXDIGIT=61;
public static final int EXPONENT=62;
public static final int SPACE_OR_TAB=63;
public static final int WS=64;
public static final int ML_COMMENT=65;
public static final int SL_COMMENT=66;
// delegates
// delegators
public VerilogLexer() {;}
public VerilogLexer(CharStream input) {
this(input, new RecognizerSharedState());
}
public VerilogLexer(CharStream input, RecognizerSharedState state) {
super(input,state);
}
public String getGrammarFileName() { return "C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g"; }
// $ANTLR start "T__67"
public final void mT__67() throws RecognitionException {
try {
int _type = T__67;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:3:7: ( 'module' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:3:9: 'module'
{
match("module"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__67"
// $ANTLR start "T__68"
public final void mT__68() throws RecognitionException {
try {
int _type = T__68;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:4:7: ( 'macromodule' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:4:9: 'macromodule'
{
match("macromodule"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__68"
// $ANTLR start "T__69"
public final void mT__69() throws RecognitionException {
try {
int _type = T__69;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:5:7: ( 'endmodule' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:5:9: 'endmodule'
{
match("endmodule"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__69"
// $ANTLR start "T__70"
public final void mT__70() throws RecognitionException {
try {
int _type = T__70;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:6:7: ( 'primitive' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:6:9: 'primitive'
{
match("primitive"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__70"
// $ANTLR start "T__71"
public final void mT__71() throws RecognitionException {
try {
int _type = T__71;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:7:7: ( 'endprimitive' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:7:9: 'endprimitive'
{
match("endprimitive"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__71"
// $ANTLR start "T__72"
public final void mT__72() throws RecognitionException {
try {
int _type = T__72;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:8:7: ( 'initial' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:8:9: 'initial'
{
match("initial"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__72"
// $ANTLR start "T__73"
public final void mT__73() throws RecognitionException {
try {
int _type = T__73;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:9:7: ( '1\\'b0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:9:9: '1\\'b0'
{
match("1'b0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__73"
// $ANTLR start "T__74"
public final void mT__74() throws RecognitionException {
try {
int _type = T__74;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:10:7: ( '1\\'b1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:10:9: '1\\'b1'
{
match("1'b1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__74"
// $ANTLR start "T__75"
public final void mT__75() throws RecognitionException {
try {
int _type = T__75;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:11:7: ( '1\\'bx' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:11:9: '1\\'bx'
{
match("1'bx"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__75"
// $ANTLR start "T__76"
public final void mT__76() throws RecognitionException {
try {
int _type = T__76;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:12:7: ( 'table' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:12:9: 'table'
{
match("table"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__76"
// $ANTLR start "T__77"
public final void mT__77() throws RecognitionException {
try {
int _type = T__77;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:13:7: ( 'endtable' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:13:9: 'endtable'
{
match("endtable"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__77"
// $ANTLR start "T__78"
public final void mT__78() throws RecognitionException {
try {
int _type = T__78;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:14:7: ( 'task' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:14:9: 'task'
{
match("task"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__78"
// $ANTLR start "T__79"
public final void mT__79() throws RecognitionException {
try {
int _type = T__79;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:15:7: ( 'endtask' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:15:9: 'endtask'
{
match("endtask"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__79"
// $ANTLR start "T__80"
public final void mT__80() throws RecognitionException {
try {
int _type = T__80;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:16:7: ( 'function' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:16:9: 'function'
{
match("function"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__80"
// $ANTLR start "T__81"
public final void mT__81() throws RecognitionException {
try {
int _type = T__81;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:17:7: ( 'endfunction' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:17:9: 'endfunction'
{
match("endfunction"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__81"
// $ANTLR start "T__82"
public final void mT__82() throws RecognitionException {
try {
int _type = T__82;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:18:7: ( 'integer' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:18:9: 'integer'
{
match("integer"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__82"
// $ANTLR start "T__83"
public final void mT__83() throws RecognitionException {
try {
int _type = T__83;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:19:7: ( 'real' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:19:9: 'real'
{
match("real"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__83"
// $ANTLR start "T__84"
public final void mT__84() throws RecognitionException {
try {
int _type = T__84;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:20:7: ( 'parameter' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:20:9: 'parameter'
{
match("parameter"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__84"
// $ANTLR start "T__85"
public final void mT__85() throws RecognitionException {
try {
int _type = T__85;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:21:7: ( 'input' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:21:9: 'input'
{
match("input"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__85"
// $ANTLR start "T__86"
public final void mT__86() throws RecognitionException {
try {
int _type = T__86;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:22:7: ( 'output' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:22:9: 'output'
{
match("output"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__86"
// $ANTLR start "T__87"
public final void mT__87() throws RecognitionException {
try {
int _type = T__87;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:23:7: ( 'inout' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:23:9: 'inout'
{
match("inout"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__87"
// $ANTLR start "T__88"
public final void mT__88() throws RecognitionException {
try {
int _type = T__88;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:24:7: ( 'wire' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:24:9: 'wire'
{
match("wire"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__88"
// $ANTLR start "T__89"
public final void mT__89() throws RecognitionException {
try {
int _type = T__89;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:25:7: ( 'tri' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:25:9: 'tri'
{
match("tri"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__89"
// $ANTLR start "T__90"
public final void mT__90() throws RecognitionException {
try {
int _type = T__90;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:26:7: ( 'tri1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:26:9: 'tri1'
{
match("tri1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__90"
// $ANTLR start "T__91"
public final void mT__91() throws RecognitionException {
try {
int _type = T__91;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:27:7: ( 'supply0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:27:9: 'supply0'
{
match("supply0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__91"
// $ANTLR start "T__92"
public final void mT__92() throws RecognitionException {
try {
int _type = T__92;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:28:7: ( 'wand' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:28:9: 'wand'
{
match("wand"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__92"
// $ANTLR start "T__93"
public final void mT__93() throws RecognitionException {
try {
int _type = T__93;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:29:7: ( 'triand' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:29:9: 'triand'
{
match("triand"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__93"
// $ANTLR start "T__94"
public final void mT__94() throws RecognitionException {
try {
int _type = T__94;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:30:7: ( 'tri0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:30:9: 'tri0'
{
match("tri0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__94"
// $ANTLR start "T__95"
public final void mT__95() throws RecognitionException {
try {
int _type = T__95;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:31:7: ( 'supply1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:31:9: 'supply1'
{
match("supply1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__95"
// $ANTLR start "T__96"
public final void mT__96() throws RecognitionException {
try {
int _type = T__96;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:32:7: ( 'wor' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:32:9: 'wor'
{
match("wor"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__96"
// $ANTLR start "T__97"
public final void mT__97() throws RecognitionException {
try {
int _type = T__97;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:33:7: ( 'trior' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:33:9: 'trior'
{
match("trior"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__97"
// $ANTLR start "T__98"
public final void mT__98() throws RecognitionException {
try {
int _type = T__98;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:34:7: ( 'scalared' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:34:9: 'scalared'
{
match("scalared"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__98"
// $ANTLR start "T__99"
public final void mT__99() throws RecognitionException {
try {
int _type = T__99;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:35:7: ( 'vectored' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:35:9: 'vectored'
{
match("vectored"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__99"
// $ANTLR start "T__100"
public final void mT__100() throws RecognitionException {
try {
int _type = T__100;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:36:8: ( 'reg' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:36:10: 'reg'
{
match("reg"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__100"
// $ANTLR start "T__101"
public final void mT__101() throws RecognitionException {
try {
int _type = T__101;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:37:8: ( 'time' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:37:10: 'time'
{
match("time"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__101"
// $ANTLR start "T__102"
public final void mT__102() throws RecognitionException {
try {
int _type = T__102;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:38:8: ( 'event' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:38:10: 'event'
{
match("event"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__102"
// $ANTLR start "T__103"
public final void mT__103() throws RecognitionException {
try {
int _type = T__103;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:39:8: ( 'defparam' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:39:10: 'defparam'
{
match("defparam"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__103"
// $ANTLR start "T__104"
public final void mT__104() throws RecognitionException {
try {
int _type = T__104;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:40:8: ( 'small' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:40:10: 'small'
{
match("small"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__104"
// $ANTLR start "T__105"
public final void mT__105() throws RecognitionException {
try {
int _type = T__105;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:41:8: ( 'medium' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:41:10: 'medium'
{
match("medium"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__105"
// $ANTLR start "T__106"
public final void mT__106() throws RecognitionException {
try {
int _type = T__106;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:42:8: ( 'large' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:42:10: 'large'
{
match("large"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__106"
// $ANTLR start "T__107"
public final void mT__107() throws RecognitionException {
try {
int _type = T__107;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:43:8: ( 'strong0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:43:10: 'strong0'
{
match("strong0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__107"
// $ANTLR start "T__108"
public final void mT__108() throws RecognitionException {
try {
int _type = T__108;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:44:8: ( 'pull0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:44:10: 'pull0'
{
match("pull0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__108"
// $ANTLR start "T__109"
public final void mT__109() throws RecognitionException {
try {
int _type = T__109;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:45:8: ( 'weak0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:45:10: 'weak0'
{
match("weak0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__109"
// $ANTLR start "T__110"
public final void mT__110() throws RecognitionException {
try {
int _type = T__110;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:46:8: ( 'highz0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:46:10: 'highz0'
{
match("highz0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__110"
// $ANTLR start "T__111"
public final void mT__111() throws RecognitionException {
try {
int _type = T__111;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:47:8: ( 'strong1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:47:10: 'strong1'
{
match("strong1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__111"
// $ANTLR start "T__112"
public final void mT__112() throws RecognitionException {
try {
int _type = T__112;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:48:8: ( 'pull1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:48:10: 'pull1'
{
match("pull1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__112"
// $ANTLR start "T__113"
public final void mT__113() throws RecognitionException {
try {
int _type = T__113;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:49:8: ( 'weak1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:49:10: 'weak1'
{
match("weak1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__113"
// $ANTLR start "T__114"
public final void mT__114() throws RecognitionException {
try {
int _type = T__114;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:50:8: ( 'highz1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:50:10: 'highz1'
{
match("highz1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__114"
// $ANTLR start "T__115"
public final void mT__115() throws RecognitionException {
try {
int _type = T__115;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:51:8: ( 'and' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:51:10: 'and'
{
match("and"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__115"
// $ANTLR start "T__116"
public final void mT__116() throws RecognitionException {
try {
int _type = T__116;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:52:8: ( 'nand' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:52:10: 'nand'
{
match("nand"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__116"
// $ANTLR start "T__117"
public final void mT__117() throws RecognitionException {
try {
int _type = T__117;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:53:8: ( 'or' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:53:10: 'or'
{
match("or"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__117"
// $ANTLR start "T__118"
public final void mT__118() throws RecognitionException {
try {
int _type = T__118;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:54:8: ( 'nor' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:54:10: 'nor'
{
match("nor"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__118"
// $ANTLR start "T__119"
public final void mT__119() throws RecognitionException {
try {
int _type = T__119;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:55:8: ( 'xor' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:55:10: 'xor'
{
match("xor"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__119"
// $ANTLR start "T__120"
public final void mT__120() throws RecognitionException {
try {
int _type = T__120;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:56:8: ( 'xnor' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:56:10: 'xnor'
{
match("xnor"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__120"
// $ANTLR start "T__121"
public final void mT__121() throws RecognitionException {
try {
int _type = T__121;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:57:8: ( 'buf' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:57:10: 'buf'
{
match("buf"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__121"
// $ANTLR start "T__122"
public final void mT__122() throws RecognitionException {
try {
int _type = T__122;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:58:8: ( 'bufif0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:58:10: 'bufif0'
{
match("bufif0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__122"
// $ANTLR start "T__123"
public final void mT__123() throws RecognitionException {
try {
int _type = T__123;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:59:8: ( 'bufif1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:59:10: 'bufif1'
{
match("bufif1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__123"
// $ANTLR start "T__124"
public final void mT__124() throws RecognitionException {
try {
int _type = T__124;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:60:8: ( 'not' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:60:10: 'not'
{
match("not"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__124"
// $ANTLR start "T__125"
public final void mT__125() throws RecognitionException {
try {
int _type = T__125;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:61:8: ( 'notif0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:61:10: 'notif0'
{
match("notif0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__125"
// $ANTLR start "T__126"
public final void mT__126() throws RecognitionException {
try {
int _type = T__126;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:62:8: ( 'notif1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:62:10: 'notif1'
{
match("notif1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__126"
// $ANTLR start "T__127"
public final void mT__127() throws RecognitionException {
try {
int _type = T__127;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:63:8: ( 'pulldown' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:63:10: 'pulldown'
{
match("pulldown"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__127"
// $ANTLR start "T__128"
public final void mT__128() throws RecognitionException {
try {
int _type = T__128;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:64:8: ( 'pullup' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:64:10: 'pullup'
{
match("pullup"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__128"
// $ANTLR start "T__129"
public final void mT__129() throws RecognitionException {
try {
int _type = T__129;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:65:8: ( 'nmos' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:65:10: 'nmos'
{
match("nmos"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__129"
// $ANTLR start "T__130"
public final void mT__130() throws RecognitionException {
try {
int _type = T__130;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:66:8: ( 'rnmos' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:66:10: 'rnmos'
{
match("rnmos"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__130"
// $ANTLR start "T__131"
public final void mT__131() throws RecognitionException {
try {
int _type = T__131;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:67:8: ( 'pmos' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:67:10: 'pmos'
{
match("pmos"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__131"
// $ANTLR start "T__132"
public final void mT__132() throws RecognitionException {
try {
int _type = T__132;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:68:8: ( 'rpmos' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:68:10: 'rpmos'
{
match("rpmos"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__132"
// $ANTLR start "T__133"
public final void mT__133() throws RecognitionException {
try {
int _type = T__133;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:69:8: ( 'cmos' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:69:10: 'cmos'
{
match("cmos"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__133"
// $ANTLR start "T__134"
public final void mT__134() throws RecognitionException {
try {
int _type = T__134;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:70:8: ( 'rcmos' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:70:10: 'rcmos'
{
match("rcmos"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__134"
// $ANTLR start "T__135"
public final void mT__135() throws RecognitionException {
try {
int _type = T__135;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:71:8: ( 'tran' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:71:10: 'tran'
{
match("tran"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__135"
// $ANTLR start "T__136"
public final void mT__136() throws RecognitionException {
try {
int _type = T__136;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:72:8: ( 'rtran' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:72:10: 'rtran'
{
match("rtran"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__136"
// $ANTLR start "T__137"
public final void mT__137() throws RecognitionException {
try {
int _type = T__137;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:73:8: ( 'tranif0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:73:10: 'tranif0'
{
match("tranif0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__137"
// $ANTLR start "T__138"
public final void mT__138() throws RecognitionException {
try {
int _type = T__138;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:74:8: ( 'rtranif0' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:74:10: 'rtranif0'
{
match("rtranif0"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__138"
// $ANTLR start "T__139"
public final void mT__139() throws RecognitionException {
try {
int _type = T__139;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:75:8: ( 'tranif1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:75:10: 'tranif1'
{
match("tranif1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__139"
// $ANTLR start "T__140"
public final void mT__140() throws RecognitionException {
try {
int _type = T__140;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:76:8: ( 'rtranif1' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:76:10: 'rtranif1'
{
match("rtranif1"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__140"
// $ANTLR start "T__141"
public final void mT__141() throws RecognitionException {
try {
int _type = T__141;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:77:8: ( 'always' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:77:10: 'always'
{
match("always"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__141"
// $ANTLR start "T__142"
public final void mT__142() throws RecognitionException {
try {
int _type = T__142;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:78:8: ( 'if' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:78:10: 'if'
{
match("if"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__142"
// $ANTLR start "T__143"
public final void mT__143() throws RecognitionException {
try {
int _type = T__143;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:79:8: ( 'else' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:79:10: 'else'
{
match("else"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__143"
// $ANTLR start "T__144"
public final void mT__144() throws RecognitionException {
try {
int _type = T__144;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:80:8: ( 'endcase' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:80:10: 'endcase'
{
match("endcase"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__144"
// $ANTLR start "T__145"
public final void mT__145() throws RecognitionException {
try {
int _type = T__145;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:81:8: ( 'case' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:81:10: 'case'
{
match("case"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__145"
// $ANTLR start "T__146"
public final void mT__146() throws RecognitionException {
try {
int _type = T__146;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:82:8: ( 'casez' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:82:10: 'casez'
{
match("casez"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__146"
// $ANTLR start "T__147"
public final void mT__147() throws RecognitionException {
try {
int _type = T__147;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:83:8: ( 'casex' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:83:10: 'casex'
{
match("casex"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__147"
// $ANTLR start "T__148"
public final void mT__148() throws RecognitionException {
try {
int _type = T__148;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:84:8: ( 'default' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:84:10: 'default'
{
match("default"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__148"
// $ANTLR start "T__149"
public final void mT__149() throws RecognitionException {
try {
int _type = T__149;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:85:8: ( 'forever' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:85:10: 'forever'
{
match("forever"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__149"
// $ANTLR start "T__150"
public final void mT__150() throws RecognitionException {
try {
int _type = T__150;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:86:8: ( 'repeat' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:86:10: 'repeat'
{
match("repeat"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__150"
// $ANTLR start "T__151"
public final void mT__151() throws RecognitionException {
try {
int _type = T__151;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:87:8: ( 'while' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:87:10: 'while'
{
match("while"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__151"
// $ANTLR start "T__152"
public final void mT__152() throws RecognitionException {
try {
int _type = T__152;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:88:8: ( 'for' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:88:10: 'for'
{
match("for"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__152"
// $ANTLR start "T__153"
public final void mT__153() throws RecognitionException {
try {
int _type = T__153;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:89:8: ( 'wait' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:89:10: 'wait'
{
match("wait"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__153"
// $ANTLR start "T__154"
public final void mT__154() throws RecognitionException {
try {
int _type = T__154;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:90:8: ( 'disable' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:90:10: 'disable'
{
match("disable"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__154"
// $ANTLR start "T__155"
public final void mT__155() throws RecognitionException {
try {
int _type = T__155;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:91:8: ( 'begin' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:91:10: 'begin'
{
match("begin"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__155"
// $ANTLR start "T__156"
public final void mT__156() throws RecognitionException {
try {
int _type = T__156;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:92:8: ( 'end' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:92:10: 'end'
{
match("end"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__156"
// $ANTLR start "T__157"
public final void mT__157() throws RecognitionException {
try {
int _type = T__157;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:93:8: ( 'fork' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:93:10: 'fork'
{
match("fork"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__157"
// $ANTLR start "T__158"
public final void mT__158() throws RecognitionException {
try {
int _type = T__158;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:94:8: ( 'join' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:94:10: 'join'
{
match("join"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__158"
// $ANTLR start "T__159"
public final void mT__159() throws RecognitionException {
try {
int _type = T__159;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:95:8: ( 'deassign' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:95:10: 'deassign'
{
match("deassign"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__159"
// $ANTLR start "T__160"
public final void mT__160() throws RecognitionException {
try {
int _type = T__160;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:96:8: ( 'force' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:96:10: 'force'
{
match("force"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__160"
// $ANTLR start "T__161"
public final void mT__161() throws RecognitionException {
try {
int _type = T__161;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:97:8: ( 'release' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:97:10: 'release'
{
match("release"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__161"
// $ANTLR start "T__162"
public final void mT__162() throws RecognitionException {
try {
int _type = T__162;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:98:8: ( 'specify' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:98:10: 'specify'
{
match("specify"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__162"
// $ANTLR start "T__163"
public final void mT__163() throws RecognitionException {
try {
int _type = T__163;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:99:8: ( 'endspecify' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:99:10: 'endspecify'
{
match("endspecify"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__163"
// $ANTLR start "T__164"
public final void mT__164() throws RecognitionException {
try {
int _type = T__164;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:100:8: ( 'specparam' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:100:10: 'specparam'
{
match("specparam"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__164"
// $ANTLR start "T__165"
public final void mT__165() throws RecognitionException {
try {
int _type = T__165;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:101:8: ( '$setup' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:101:10: '$setup'
{
match("$setup"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__165"
// $ANTLR start "T__166"
public final void mT__166() throws RecognitionException {
try {
int _type = T__166;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:102:8: ( '$hold' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:102:10: '$hold'
{
match("$hold"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__166"
// $ANTLR start "T__167"
public final void mT__167() throws RecognitionException {
try {
int _type = T__167;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:103:8: ( '$period' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:103:10: '$period'
{
match("$period"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__167"
// $ANTLR start "T__168"
public final void mT__168() throws RecognitionException {
try {
int _type = T__168;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:104:8: ( '$width' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:104:10: '$width'
{
match("$width"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__168"
// $ANTLR start "T__169"
public final void mT__169() throws RecognitionException {
try {
int _type = T__169;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:105:8: ( '$skew' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:105:10: '$skew'
{
match("$skew"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__169"
// $ANTLR start "T__170"
public final void mT__170() throws RecognitionException {
try {
int _type = T__170;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:106:8: ( '$recovery' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:106:10: '$recovery'
{
match("$recovery"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__170"
// $ANTLR start "T__171"
public final void mT__171() throws RecognitionException {
try {
int _type = T__171;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:107:8: ( '$setuphold' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:107:10: '$setuphold'
{
match("$setuphold"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__171"
// $ANTLR start "T__172"
public final void mT__172() throws RecognitionException {
try {
int _type = T__172;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:108:8: ( '&&&' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:108:10: '&&&'
{
match("&&&"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__172"
// $ANTLR start "T__173"
public final void mT__173() throws RecognitionException {
try {
int _type = T__173;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:109:8: ( 'posedge' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:109:10: 'posedge'
{
match("posedge"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__173"
// $ANTLR start "T__174"
public final void mT__174() throws RecognitionException {
try {
int _type = T__174;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:110:8: ( 'negedge' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:110:10: 'negedge'
{
match("negedge"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__174"
// $ANTLR start "T__175"
public final void mT__175() throws RecognitionException {
try {
int _type = T__175;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:111:8: ( 'edge' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:111:10: 'edge'
{
match("edge"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__175"
// $ANTLR start "T__176"
public final void mT__176() throws RecognitionException {
try {
int _type = T__176;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:112:8: ( '0x' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:112:10: '0x'
{
match("0x"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__176"
// $ANTLR start "T__177"
public final void mT__177() throws RecognitionException {
try {
int _type = T__177;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:113:8: ( '1x' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:113:10: '1x'
{
match("1x"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__177"
// $ANTLR start "T__178"
public final void mT__178() throws RecognitionException {
try {
int _type = T__178;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:114:8: ( '`define' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:114:10: '`define'
{
match("`define"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__178"
// $ANTLR start "T__179"
public final void mT__179() throws RecognitionException {
try {
int _type = T__179;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:115:8: ( '`include' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:115:10: '`include'
{
match("`include"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "T__179"
// $ANTLR start "KW_ASSIGN"
public final void mKW_ASSIGN() throws RecognitionException {
try {
int _type = KW_ASSIGN;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:933:14: ( 'assign' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:933:16: 'assign'
{
match("assign"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "KW_ASSIGN"
// $ANTLR start "KW_TRIREG"
public final void mKW_TRIREG() throws RecognitionException {
try {
int _type = KW_TRIREG;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:934:14: ( 'trireg' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:934:16: 'trireg'
{
match("trireg"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "KW_TRIREG"
// $ANTLR start "AT"
public final void mAT() throws RecognitionException {
try {
int _type = AT;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1022:8: ( '@' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1022:10: '@'
{
match('@'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "AT"
// $ANTLR start "COLON"
public final void mCOLON() throws RecognitionException {
try {
int _type = COLON;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1023:11: ( ':' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1023:13: ':'
{
match(':'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "COLON"
// $ANTLR start "COMMA"
public final void mCOMMA() throws RecognitionException {
try {
int _type = COMMA;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1024:11: ( ',' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1024:13: ','
{
match(','); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "COMMA"
// $ANTLR start "DOT"
public final void mDOT() throws RecognitionException {
try {
int _type = DOT;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1025:9: ( '.' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1025:11: '.'
{
match('.'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "DOT"
// $ANTLR start "ASSIGN"
public final void mASSIGN() throws RecognitionException {
try {
int _type = ASSIGN;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1026:12: ( '=' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1026:14: '='
{
match('='); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "ASSIGN"
// $ANTLR start "MINUS"
public final void mMINUS() throws RecognitionException {
try {
int _type = MINUS;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1027:11: ( '-' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1027:13: '-'
{
match('-'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "MINUS"
// $ANTLR start "LBRACK"
public final void mLBRACK() throws RecognitionException {
try {
int _type = LBRACK;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1028:12: ( '[' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1028:14: '['
{
match('['); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "LBRACK"
// $ANTLR start "RBRACK"
public final void mRBRACK() throws RecognitionException {
try {
int _type = RBRACK;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1029:12: ( ']' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1029:14: ']'
{
match(']'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "RBRACK"
// $ANTLR start "LCURLY"
public final void mLCURLY() throws RecognitionException {
try {
int _type = LCURLY;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1030:12: ( '{' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1030:14: '{'
{
match('{'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "LCURLY"
// $ANTLR start "RCURLY"
public final void mRCURLY() throws RecognitionException {
try {
int _type = RCURLY;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1031:12: ( '}' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1031:14: '}'
{
match('}'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "RCURLY"
// $ANTLR start "LPAREN"
public final void mLPAREN() throws RecognitionException {
try {
int _type = LPAREN;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1032:12: ( '(' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1032:14: '('
{
match('('); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "LPAREN"
// $ANTLR start "RPAREN"
public final void mRPAREN() throws RecognitionException {
try {
int _type = RPAREN;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1033:12: ( ')' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1033:14: ')'
{
match(')'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "RPAREN"
// $ANTLR start "POUND"
public final void mPOUND() throws RecognitionException {
try {
int _type = POUND;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1034:11: ( '#' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1034:13: '#'
{
match('#'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "POUND"
// $ANTLR start "QUESTION"
public final void mQUESTION() throws RecognitionException {
try {
int _type = QUESTION;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1035:13: ( '?' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1035:15: '?'
{
match('?'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "QUESTION"
// $ANTLR start "SEMI"
public final void mSEMI() throws RecognitionException {
try {
int _type = SEMI;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1036:10: ( ';' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1036:12: ';'
{
match(';'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "SEMI"
// $ANTLR start "PLUS"
public final void mPLUS() throws RecognitionException {
try {
int _type = PLUS;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1037:13: ( '+' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1037:15: '+'
{
match('+'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "PLUS"
// $ANTLR start "LNOT"
public final void mLNOT() throws RecognitionException {
try {
int _type = LNOT;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1038:13: ( '!' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1038:15: '!'
{
match('!'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "LNOT"
// $ANTLR start "BNOT"
public final void mBNOT() throws RecognitionException {
try {
int _type = BNOT;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1039:13: ( '~' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1039:15: '~'
{
match('~'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "BNOT"
// $ANTLR start "BAND"
public final void mBAND() throws RecognitionException {
try {
int _type = BAND;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1040:13: ( '&' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1040:15: '&'
{
match('&'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "BAND"
// $ANTLR start "RNAND"
public final void mRNAND() throws RecognitionException {
try {
int _type = RNAND;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1041:13: ( '~&' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1041:15: '~&'
{
match("~&"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "RNAND"
// $ANTLR start "BOR"
public final void mBOR() throws RecognitionException {
try {
int _type = BOR;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1042:13: ( '|' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1042:15: '|'
{
match('|'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "BOR"
// $ANTLR start "RNOR"
public final void mRNOR() throws RecognitionException {
try {
int _type = RNOR;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1043:13: ( '~|' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1043:15: '~|'
{
match("~|"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "RNOR"
// $ANTLR start "BXOR"
public final void mBXOR() throws RecognitionException {
try {
int _type = BXOR;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1044:13: ( '^' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1044:15: '^'
{
match('^'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "BXOR"
// $ANTLR start "BXNOR"
public final void mBXNOR() throws RecognitionException {
try {
int _type = BXNOR;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1045:13: ( '~^' | '^~' )
int alt1=2;
int LA1_0 = input.LA(1);
if ( (LA1_0=='~') ) {
alt1=1;
}
else if ( (LA1_0=='^') ) {
alt1=2;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
NoViableAltException nvae =
new NoViableAltException("", 1, 0, input);
throw nvae;
}
switch (alt1) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1045:15: '~^'
{
match("~^"); if (state.failed) return ;
}
break;
case 2 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1045:22: '^~'
{
match("^~"); if (state.failed) return ;
}
break;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "BXNOR"
// $ANTLR start "STAR"
public final void mSTAR() throws RecognitionException {
try {
int _type = STAR;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1046:13: ( '*' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1046:15: '*'
{
match('*'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "STAR"
// $ANTLR start "DIV"
public final void mDIV() throws RecognitionException {
try {
int _type = DIV;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1047:13: ( '/' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1047:15: '/'
{
match('/'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "DIV"
// $ANTLR start "MOD"
public final void mMOD() throws RecognitionException {
try {
int _type = MOD;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1048:13: ( '%' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1048:15: '%'
{
match('%'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "MOD"
// $ANTLR start "EQUAL"
public final void mEQUAL() throws RecognitionException {
try {
int _type = EQUAL;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1049:13: ( '==' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1049:15: '=='
{
match("=="); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "EQUAL"
// $ANTLR start "NOT_EQ"
public final void mNOT_EQ() throws RecognitionException {
try {
int _type = NOT_EQ;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1050:13: ( '!=' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1050:15: '!='
{
match("!="); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "NOT_EQ"
// $ANTLR start "NOT_EQ_CASE"
public final void mNOT_EQ_CASE() throws RecognitionException {
try {
int _type = NOT_EQ_CASE;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1051:13: ( '!==' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1051:15: '!=='
{
match("!=="); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "NOT_EQ_CASE"
// $ANTLR start "EQ_CASE"
public final void mEQ_CASE() throws RecognitionException {
try {
int _type = EQ_CASE;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1052:13: ( '===' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1052:15: '==='
{
match("==="); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "EQ_CASE"
// $ANTLR start "LAND"
public final void mLAND() throws RecognitionException {
try {
int _type = LAND;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1053:13: ( '&&' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1053:15: '&&'
{
match("&&"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "LAND"
// $ANTLR start "LOR"
public final void mLOR() throws RecognitionException {
try {
int _type = LOR;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1054:13: ( '||' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1054:15: '||'
{
match("||"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "LOR"
// $ANTLR start "LT_"
public final void mLT_() throws RecognitionException {
try {
int _type = LT_;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1055:13: ( '<' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1055:15: '<'
{
match('<'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "LT_"
// $ANTLR start "LE"
public final void mLE() throws RecognitionException {
try {
int _type = LE;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1056:13: ( '<=' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1056:15: '<='
{
match("<="); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "LE"
// $ANTLR start "GT"
public final void mGT() throws RecognitionException {
try {
int _type = GT;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1057:13: ( '>' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1057:15: '>'
{
match('>'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "GT"
// $ANTLR start "GE"
public final void mGE() throws RecognitionException {
try {
int _type = GE;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1058:13: ( '>=' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1058:15: '>='
{
match(">="); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "GE"
// $ANTLR start "SR"
public final void mSR() throws RecognitionException {
try {
int _type = SR;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1059:13: ( '>>' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1059:15: '>>'
{
match(">>"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "SR"
// $ANTLR start "SL"
public final void mSL() throws RecognitionException {
try {
int _type = SL;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1060:13: ( '<<' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1060:15: '<<'
{
match("<<"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "SL"
// $ANTLR start "TRIGGER"
public final void mTRIGGER() throws RecognitionException {
try {
int _type = TRIGGER;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1061:13: ( '->' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1061:15: '->'
{
match("->"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "TRIGGER"
// $ANTLR start "PPATH"
public final void mPPATH() throws RecognitionException {
try {
int _type = PPATH;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1062:13: ( '=>' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1062:15: '=>'
{
match("=>"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "PPATH"
// $ANTLR start "FPATH"
public final void mFPATH() throws RecognitionException {
try {
int _type = FPATH;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1063:13: ( '*>' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1063:15: '*>'
{
match("*>"); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "FPATH"
// $ANTLR start "IDENTIFIER"
public final void mIDENTIFIER() throws RecognitionException {
try {
int _type = IDENTIFIER;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1070:5: ( ( 'a' .. 'z' | 'A' .. 'Z' | '_' ) ( 'a' .. 'z' | 'A' .. 'Z' | '_' | '$' | '0' .. '9' )* )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1071:9: ( 'a' .. 'z' | 'A' .. 'Z' | '_' ) ( 'a' .. 'z' | 'A' .. 'Z' | '_' | '$' | '0' .. '9' )*
{
if ( (input.LA(1)>='A' && input.LA(1)<='Z')||input.LA(1)=='_'||(input.LA(1)>='a' && input.LA(1)<='z') ) {
input.consume();
state.failed=false;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
MismatchedSetException mse = new MismatchedSetException(null,input);
recover(mse);
throw mse;}
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1071:33: ( 'a' .. 'z' | 'A' .. 'Z' | '_' | '$' | '0' .. '9' )*
loop2:
do {
int alt2=2;
int LA2_0 = input.LA(1);
if ( (LA2_0=='$'||(LA2_0>='0' && LA2_0<='9')||(LA2_0>='A' && LA2_0<='Z')||LA2_0=='_'||(LA2_0>='a' && LA2_0<='z')) ) {
alt2=1;
}
switch (alt2) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:
{
if ( input.LA(1)=='$'||(input.LA(1)>='0' && input.LA(1)<='9')||(input.LA(1)>='A' && input.LA(1)<='Z')||input.LA(1)=='_'||(input.LA(1)>='a' && input.LA(1)<='z') ) {
input.consume();
state.failed=false;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
MismatchedSetException mse = new MismatchedSetException(null,input);
recover(mse);
throw mse;}
}
break;
default :
break loop2;
}
} while (true);
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "IDENTIFIER"
// $ANTLR start "ESCAPED_IDENTIFIER"
public final void mESCAPED_IDENTIFIER() throws RecognitionException {
try {
int _type = ESCAPED_IDENTIFIER;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1079:20: ( '\\\\' (~ '\\u0020' )+ ( '\\u0020' | '\\t' | '\\n' ) )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1080:9: '\\\\' (~ '\\u0020' )+ ( '\\u0020' | '\\t' | '\\n' )
{
match('\\'); if (state.failed) return ;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1080:14: (~ '\\u0020' )+
int cnt3=0;
loop3:
do {
int alt3=2;
int LA3_0 = input.LA(1);
if ( ((LA3_0>='\t' && LA3_0<='\n')) ) {
int LA3_1 = input.LA(2);
if ( ((LA3_1>='\u0000' && LA3_1<='\uFFFF')) ) {
alt3=1;
}
}
else if ( ((LA3_0>='\u0000' && LA3_0<='\b')||(LA3_0>='\u000B' && LA3_0<='\u001F')||(LA3_0>='!' && LA3_0<='\uFFFF')) ) {
alt3=1;
}
switch (alt3) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1080:15: ~ '\\u0020'
{
if ( (input.LA(1)>='\u0000' && input.LA(1)<='\u001F')||(input.LA(1)>='!' && input.LA(1)<='\uFFFF') ) {
input.consume();
state.failed=false;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
MismatchedSetException mse = new MismatchedSetException(null,input);
recover(mse);
throw mse;}
}
break;
default :
if ( cnt3 >= 1 ) break loop3;
if (state.backtracking>0) {state.failed=true; return ;}
EarlyExitException eee =
new EarlyExitException(3, input);
throw eee;
}
cnt3++;
} while (true);
if ( (input.LA(1)>='\t' && input.LA(1)<='\n')||input.LA(1)==' ' ) {
input.consume();
state.failed=false;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
MismatchedSetException mse = new MismatchedSetException(null,input);
recover(mse);
throw mse;}
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "ESCAPED_IDENTIFIER"
// $ANTLR start "SYSTEM_TASK_NAME"
public final void mSYSTEM_TASK_NAME() throws RecognitionException {
try {
int _type = SYSTEM_TASK_NAME;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1083:18: ( '$' IDENTIFIER )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1084:9: '$' IDENTIFIER
{
match('$'); if (state.failed) return ;
mIDENTIFIER(); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "SYSTEM_TASK_NAME"
// $ANTLR start "STRING"
public final void mSTRING() throws RecognitionException {
try {
int _type = STRING;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1088:8: ( '\"' (~ ( '\"' | '\\n' ) )* '\"' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1089:9: '\"' (~ ( '\"' | '\\n' ) )* '\"'
{
match('\"'); if (state.failed) return ;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1089:13: (~ ( '\"' | '\\n' ) )*
loop4:
do {
int alt4=2;
int LA4_0 = input.LA(1);
if ( ((LA4_0>='\u0000' && LA4_0<='\t')||(LA4_0>='\u000B' && LA4_0<='!')||(LA4_0>='#' && LA4_0<='\uFFFF')) ) {
alt4=1;
}
switch (alt4) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1089:14: ~ ( '\"' | '\\n' )
{
if ( (input.LA(1)>='\u0000' && input.LA(1)<='\t')||(input.LA(1)>='\u000B' && input.LA(1)<='!')||(input.LA(1)>='#' && input.LA(1)<='\uFFFF') ) {
input.consume();
state.failed=false;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
MismatchedSetException mse = new MismatchedSetException(null,input);
recover(mse);
throw mse;}
}
break;
default :
break loop4;
}
} while (true);
match('\"'); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "STRING"
// $ANTLR start "DEFINE"
public final void mDEFINE() throws RecognitionException {
try {
int _type = DEFINE;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1095:5: ( '`' IDENTIFIER )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1096:2: '`' IDENTIFIER
{
match('`'); if (state.failed) return ;
mIDENTIFIER(); if (state.failed) return ;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "DEFINE"
// $ANTLR start "VOCAB"
public final void mVOCAB() throws RecognitionException {
try {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1102:7: ( '\\u0003' .. '\\u007F' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1103:9: '\\u0003' .. '\\u007F'
{
matchRange('\u0003','\u007F'); if (state.failed) return ;
}
}
finally {
}
}
// $ANTLR end "VOCAB"
// $ANTLR start "NUMBER"
public final void mNUMBER() throws RecognitionException {
try {
int _type = NUMBER;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1107:8: ( ( ( SIZE )? BASE SIZED_DIGIT )=> SIZED_NUMBER | UNSIZED_NUMBER )
int alt5=2;
alt5 = dfa5.predict(input);
switch (alt5) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1108:2: ( ( SIZE )? BASE SIZED_DIGIT )=> SIZED_NUMBER
{
mSIZED_NUMBER(); if (state.failed) return ;
}
break;
case 2 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1109:2: UNSIZED_NUMBER
{
mUNSIZED_NUMBER(); if (state.failed) return ;
}
break;
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "NUMBER"
// $ANTLR start "SIZED_NUMBER"
public final void mSIZED_NUMBER() throws RecognitionException {
try {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1113:14: ( ( SIZE )? BASE SIZED_DIGIT ( SIZED_DIGIT | '_' )* )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1114:2: ( SIZE )? BASE SIZED_DIGIT ( SIZED_DIGIT | '_' )*
{
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1114:2: ( SIZE )?
int alt6=2;
int LA6_0 = input.LA(1);
if ( ((LA6_0>='0' && LA6_0<='9')) ) {
alt6=1;
}
switch (alt6) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1114:3: SIZE
{
mSIZE(); if (state.failed) return ;
}
break;
}
mBASE(); if (state.failed) return ;
mSIZED_DIGIT(); if (state.failed) return ;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1114:27: ( SIZED_DIGIT | '_' )*
loop7:
do {
int alt7=3;
int LA7_0 = input.LA(1);
if ( ((LA7_0>='0' && LA7_0<='9')||LA7_0=='?'||(LA7_0>='A' && LA7_0<='F')||LA7_0=='X'||LA7_0=='Z'||(LA7_0>='a' && LA7_0<='f')||LA7_0=='x'||LA7_0=='z') ) {
alt7=1;
}
else if ( (LA7_0=='_') ) {
alt7=2;
}
switch (alt7) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1114:28: SIZED_DIGIT
{
mSIZED_DIGIT(); if (state.failed) return ;
}
break;
case 2 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1114:42: '_'
{
match('_'); if (state.failed) return ;
}
break;
default :
break loop7;
}
} while (true);
}
}
finally {
}
}
// $ANTLR end "SIZED_NUMBER"
// $ANTLR start "SIZE"
public final void mSIZE() throws RecognitionException {
try {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1118:6: ( ( DIGIT )+ )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1119:2: ( DIGIT )+
{
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1119:2: ( DIGIT )+
int cnt8=0;
loop8:
do {
int alt8=2;
int LA8_0 = input.LA(1);
if ( ((LA8_0>='0' && LA8_0<='9')) ) {
alt8=1;
}
switch (alt8) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1119:3: DIGIT
{
mDIGIT(); if (state.failed) return ;
}
break;
default :
if ( cnt8 >= 1 ) break loop8;
if (state.backtracking>0) {state.failed=true; return ;}
EarlyExitException eee =
new EarlyExitException(8, input);
throw eee;
}
cnt8++;
} while (true);
}
}
finally {
}
}
// $ANTLR end "SIZE"
// $ANTLR start "BASE"
public final void mBASE() throws RecognitionException {
try {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1123:6: ( '\\'' ( 'd' | 'D' | 'h' | 'H' | 'o' | 'O' | 'b' | 'B' ) )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1124:2: '\\'' ( 'd' | 'D' | 'h' | 'H' | 'o' | 'O' | 'b' | 'B' )
{
match('\''); if (state.failed) return ;
if ( input.LA(1)=='B'||input.LA(1)=='D'||input.LA(1)=='H'||input.LA(1)=='O'||input.LA(1)=='b'||input.LA(1)=='d'||input.LA(1)=='h'||input.LA(1)=='o' ) {
input.consume();
state.failed=false;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
MismatchedSetException mse = new MismatchedSetException(null,input);
recover(mse);
throw mse;}
}
}
finally {
}
}
// $ANTLR end "BASE"
// $ANTLR start "SIZED_DIGIT"
public final void mSIZED_DIGIT() throws RecognitionException {
try {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1128:13: ( DIGIT | HEXDIGIT | 'x' | 'X' | 'z' | 'Z' | '?' )
int alt9=7;
switch ( input.LA(1) ) {
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
alt9=1;
}
break;
case 'A':
case 'B':
case 'C':
case 'D':
case 'E':
case 'F':
case 'a':
case 'b':
case 'c':
case 'd':
case 'e':
case 'f':
{
alt9=2;
}
break;
case 'x':
{
alt9=3;
}
break;
case 'X':
{
alt9=4;
}
break;
case 'z':
{
alt9=5;
}
break;
case 'Z':
{
alt9=6;
}
break;
case '?':
{
alt9=7;
}
break;
default:
if (state.backtracking>0) {state.failed=true; return ;}
NoViableAltException nvae =
new NoViableAltException("", 9, 0, input);
throw nvae;
}
switch (alt9) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1129:2: DIGIT
{
mDIGIT(); if (state.failed) return ;
}
break;
case 2 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1129:10: HEXDIGIT
{
mHEXDIGIT(); if (state.failed) return ;
}
break;
case 3 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1129:21: 'x'
{
match('x'); if (state.failed) return ;
}
break;
case 4 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1129:27: 'X'
{
match('X'); if (state.failed) return ;
}
break;
case 5 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1129:33: 'z'
{
match('z'); if (state.failed) return ;
}
break;
case 6 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1129:39: 'Z'
{
match('Z'); if (state.failed) return ;
}
break;
case 7 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1129:45: '?'
{
match('?'); if (state.failed) return ;
}
break;
}
}
finally {
}
}
// $ANTLR end "SIZED_DIGIT"
// $ANTLR start "UNSIZED_NUMBER"
public final void mUNSIZED_NUMBER() throws RecognitionException {
try {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1133:16: ( DIGIT ( DIGIT | '_' )* ( '.' ( DIGIT | '_' )* )? ( EXPONENT )? )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:2: DIGIT ( DIGIT | '_' )* ( '.' ( DIGIT | '_' )* )? ( EXPONENT )?
{
mDIGIT(); if (state.failed) return ;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:8: ( DIGIT | '_' )*
loop10:
do {
int alt10=3;
int LA10_0 = input.LA(1);
if ( ((LA10_0>='0' && LA10_0<='9')) ) {
alt10=1;
}
else if ( (LA10_0=='_') ) {
alt10=2;
}
switch (alt10) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:9: DIGIT
{
mDIGIT(); if (state.failed) return ;
}
break;
case 2 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:17: '_'
{
match('_'); if (state.failed) return ;
}
break;
default :
break loop10;
}
} while (true);
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:23: ( '.' ( DIGIT | '_' )* )?
int alt12=2;
int LA12_0 = input.LA(1);
if ( (LA12_0=='.') ) {
alt12=1;
}
switch (alt12) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:25: '.' ( DIGIT | '_' )*
{
match('.'); if (state.failed) return ;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:29: ( DIGIT | '_' )*
loop11:
do {
int alt11=3;
int LA11_0 = input.LA(1);
if ( ((LA11_0>='0' && LA11_0<='9')) ) {
alt11=1;
}
else if ( (LA11_0=='_') ) {
alt11=2;
}
switch (alt11) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:30: DIGIT
{
mDIGIT(); if (state.failed) return ;
}
break;
case 2 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:38: '_'
{
match('_'); if (state.failed) return ;
}
break;
default :
break loop11;
}
} while (true);
}
break;
}
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:47: ( EXPONENT )?
int alt13=2;
int LA13_0 = input.LA(1);
if ( (LA13_0=='E'||LA13_0=='e') ) {
alt13=1;
}
switch (alt13) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1134:48: EXPONENT
{
mEXPONENT(); if (state.failed) return ;
}
break;
}
}
}
finally {
}
}
// $ANTLR end "UNSIZED_NUMBER"
// $ANTLR start "DIGIT"
public final void mDIGIT() throws RecognitionException {
try {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1138:7: ( ( '0' .. '9' ) )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1139:9: ( '0' .. '9' )
{
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1139:9: ( '0' .. '9' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1139:10: '0' .. '9'
{
matchRange('0','9'); if (state.failed) return ;
}
}
}
finally {
}
}
// $ANTLR end "DIGIT"
// $ANTLR start "HEXDIGIT"
public final void mHEXDIGIT() throws RecognitionException {
try {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1143:10: ( ( 'A' .. 'F' | 'a' .. 'f' ) )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1144:9: ( 'A' .. 'F' | 'a' .. 'f' )
{
if ( (input.LA(1)>='A' && input.LA(1)<='F')||(input.LA(1)>='a' && input.LA(1)<='f') ) {
input.consume();
state.failed=false;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
MismatchedSetException mse = new MismatchedSetException(null,input);
recover(mse);
throw mse;}
}
}
finally {
}
}
// $ANTLR end "HEXDIGIT"
// $ANTLR start "EXPONENT"
public final void mEXPONENT() throws RecognitionException {
try {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1148:10: ( ( 'e' | 'E' ) ( '+' | '-' )? ( '0' .. '9' )+ )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1149:9: ( 'e' | 'E' ) ( '+' | '-' )? ( '0' .. '9' )+
{
if ( input.LA(1)=='E'||input.LA(1)=='e' ) {
input.consume();
state.failed=false;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
MismatchedSetException mse = new MismatchedSetException(null,input);
recover(mse);
throw mse;}
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1149:19: ( '+' | '-' )?
int alt14=2;
int LA14_0 = input.LA(1);
if ( (LA14_0=='+'||LA14_0=='-') ) {
alt14=1;
}
switch (alt14) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:
{
if ( input.LA(1)=='+'||input.LA(1)=='-' ) {
input.consume();
state.failed=false;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
MismatchedSetException mse = new MismatchedSetException(null,input);
recover(mse);
throw mse;}
}
break;
}
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1149:30: ( '0' .. '9' )+
int cnt15=0;
loop15:
do {
int alt15=2;
int LA15_0 = input.LA(1);
if ( ((LA15_0>='0' && LA15_0<='9')) ) {
alt15=1;
}
switch (alt15) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1149:31: '0' .. '9'
{
matchRange('0','9'); if (state.failed) return ;
}
break;
default :
if ( cnt15 >= 1 ) break loop15;
if (state.backtracking>0) {state.failed=true; return ;}
EarlyExitException eee =
new EarlyExitException(15, input);
throw eee;
}
cnt15++;
} while (true);
}
}
finally {
}
}
// $ANTLR end "EXPONENT"
// $ANTLR start "SPACE_OR_TAB"
public final void mSPACE_OR_TAB() throws RecognitionException {
try {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1153:2: ( ( ' ' | '\\t' )+ )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1153:4: ( ' ' | '\\t' )+
{
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1153:4: ( ' ' | '\\t' )+
int cnt16=0;
loop16:
do {
int alt16=2;
int LA16_0 = input.LA(1);
if ( (LA16_0=='\t'||LA16_0==' ') ) {
alt16=1;
}
switch (alt16) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:
{
if ( input.LA(1)=='\t'||input.LA(1)==' ' ) {
input.consume();
state.failed=false;
}
else {
if (state.backtracking>0) {state.failed=true; return ;}
MismatchedSetException mse = new MismatchedSetException(null,input);
recover(mse);
throw mse;}
}
break;
default :
if ( cnt16 >= 1 ) break loop16;
if (state.backtracking>0) {state.failed=true; return ;}
EarlyExitException eee =
new EarlyExitException(16, input);
throw eee;
}
cnt16++;
} while (true);
}
}
finally {
}
}
// $ANTLR end "SPACE_OR_TAB"
// $ANTLR start "WS"
public final void mWS() throws RecognitionException {
try {
int _type = WS;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1160:2: ( ( SPACE_OR_TAB )+ )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1160:4: ( SPACE_OR_TAB )+
{
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1160:4: ( SPACE_OR_TAB )+
int cnt17=0;
loop17:
do {
int alt17=2;
int LA17_0 = input.LA(1);
if ( (LA17_0=='\t'||LA17_0==' ') ) {
alt17=1;
}
switch (alt17) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1160:4: SPACE_OR_TAB
{
mSPACE_OR_TAB(); if (state.failed) return ;
}
break;
default :
if ( cnt17 >= 1 ) break loop17;
if (state.backtracking>0) {state.failed=true; return ;}
EarlyExitException eee =
new EarlyExitException(17, input);
throw eee;
}
cnt17++;
} while (true);
if ( state.backtracking==0 ) {
_channel=HIDDEN;
}
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "WS"
// $ANTLR start "ML_COMMENT"
public final void mML_COMMENT() throws RecognitionException {
try {
int _type = ML_COMMENT;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1165:5: ( '/*' ( options {greedy=false; } : . )* '*/' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1165:9: '/*' ( options {greedy=false; } : . )* '*/'
{
match("/*"); if (state.failed) return ;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1165:14: ( options {greedy=false; } : . )*
loop18:
do {
int alt18=2;
int LA18_0 = input.LA(1);
if ( (LA18_0=='*') ) {
int LA18_1 = input.LA(2);
if ( (LA18_1=='/') ) {
alt18=2;
}
else if ( ((LA18_1>='\u0000' && LA18_1<='.')||(LA18_1>='0' && LA18_1<='\uFFFF')) ) {
alt18=1;
}
}
else if ( ((LA18_0>='\u0000' && LA18_0<=')')||(LA18_0>='+' && LA18_0<='\uFFFF')) ) {
alt18=1;
}
switch (alt18) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1165:42: .
{
matchAny(); if (state.failed) return ;
}
break;
default :
break loop18;
}
} while (true);
match("*/"); if (state.failed) return ;
if ( state.backtracking==0 ) {
_channel=HIDDEN;
}
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "ML_COMMENT"
// $ANTLR start "SL_COMMENT"
public final void mSL_COMMENT() throws RecognitionException {
try {
int _type = SL_COMMENT;
int _channel = DEFAULT_TOKEN_CHANNEL;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1169:5: ( '//' ( options {greedy=false; } : . )* ( '\\r' )? '\\n' )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1169:7: '//' ( options {greedy=false; } : . )* ( '\\r' )? '\\n'
{
match("//"); if (state.failed) return ;
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1169:13: ( options {greedy=false; } : . )*
loop19:
do {
int alt19=2;
int LA19_0 = input.LA(1);
if ( (LA19_0=='\r') ) {
alt19=2;
}
else if ( (LA19_0=='\n') ) {
alt19=2;
}
else if ( ((LA19_0>='\u0000' && LA19_0<='\t')||(LA19_0>='\u000B' && LA19_0<='\f')||(LA19_0>='\u000E' && LA19_0<='\uFFFF')) ) {
alt19=1;
}
switch (alt19) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1169:41: .
{
matchAny(); if (state.failed) return ;
}
break;
default :
break loop19;
}
} while (true);
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1169:47: ( '\\r' )?
int alt20=2;
int LA20_0 = input.LA(1);
if ( (LA20_0=='\r') ) {
alt20=1;
}
switch (alt20) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1169:47: '\\r'
{
match('\r'); if (state.failed) return ;
}
break;
}
match('\n'); if (state.failed) return ;
if ( state.backtracking==0 ) {
_channel=HIDDEN;
}
}
state.type = _type;
state.channel = _channel;
}
finally {
}
}
// $ANTLR end "SL_COMMENT"
public void mTokens() throws RecognitionException {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:8: ( T__67 | T__68 | T__69 | T__70 | T__71 | T__72 | T__73 | T__74 | T__75 | T__76 | T__77 | T__78 | T__79 | T__80 | T__81 | T__82 | T__83 | T__84 | T__85 | T__86 | T__87 | T__88 | T__89 | T__90 | T__91 | T__92 | T__93 | T__94 | T__95 | T__96 | T__97 | T__98 | T__99 | T__100 | T__101 | T__102 | T__103 | T__104 | T__105 | T__106 | T__107 | T__108 | T__109 | T__110 | T__111 | T__112 | T__113 | T__114 | T__115 | T__116 | T__117 | T__118 | T__119 | T__120 | T__121 | T__122 | T__123 | T__124 | T__125 | T__126 | T__127 | T__128 | T__129 | T__130 | T__131 | T__132 | T__133 | T__134 | T__135 | T__136 | T__137 | T__138 | T__139 | T__140 | T__141 | T__142 | T__143 | T__144 | T__145 | T__146 | T__147 | T__148 | T__149 | T__150 | T__151 | T__152 | T__153 | T__154 | T__155 | T__156 | T__157 | T__158 | T__159 | T__160 | T__161 | T__162 | T__163 | T__164 | T__165 | T__166 | T__167 | T__168 | T__169 | T__170 | T__171 | T__172 | T__173 | T__174 | T__175 | T__176 | T__177 | T__178 | T__179 | KW_ASSIGN | KW_TRIREG | AT | COLON | COMMA | DOT | ASSIGN | MINUS | LBRACK | RBRACK | LCURLY | RCURLY | LPAREN | RPAREN | POUND | QUESTION | SEMI | PLUS | LNOT | BNOT | BAND | RNAND | BOR | RNOR | BXOR | BXNOR | STAR | DIV | MOD | EQUAL | NOT_EQ | NOT_EQ_CASE | EQ_CASE | LAND | LOR | LT_ | LE | GT | GE | SR | SL | TRIGGER | PPATH | FPATH | IDENTIFIER | ESCAPED_IDENTIFIER | SYSTEM_TASK_NAME | STRING | DEFINE | NUMBER | WS | ML_COMMENT | SL_COMMENT )
int alt21=166;
alt21 = dfa21.predict(input);
switch (alt21) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:10: T__67
{
mT__67(); if (state.failed) return ;
}
break;
case 2 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:16: T__68
{
mT__68(); if (state.failed) return ;
}
break;
case 3 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:22: T__69
{
mT__69(); if (state.failed) return ;
}
break;
case 4 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:28: T__70
{
mT__70(); if (state.failed) return ;
}
break;
case 5 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:34: T__71
{
mT__71(); if (state.failed) return ;
}
break;
case 6 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:40: T__72
{
mT__72(); if (state.failed) return ;
}
break;
case 7 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:46: T__73
{
mT__73(); if (state.failed) return ;
}
break;
case 8 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:52: T__74
{
mT__74(); if (state.failed) return ;
}
break;
case 9 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:58: T__75
{
mT__75(); if (state.failed) return ;
}
break;
case 10 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:64: T__76
{
mT__76(); if (state.failed) return ;
}
break;
case 11 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:70: T__77
{
mT__77(); if (state.failed) return ;
}
break;
case 12 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:76: T__78
{
mT__78(); if (state.failed) return ;
}
break;
case 13 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:82: T__79
{
mT__79(); if (state.failed) return ;
}
break;
case 14 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:88: T__80
{
mT__80(); if (state.failed) return ;
}
break;
case 15 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:94: T__81
{
mT__81(); if (state.failed) return ;
}
break;
case 16 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:100: T__82
{
mT__82(); if (state.failed) return ;
}
break;
case 17 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:106: T__83
{
mT__83(); if (state.failed) return ;
}
break;
case 18 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:112: T__84
{
mT__84(); if (state.failed) return ;
}
break;
case 19 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:118: T__85
{
mT__85(); if (state.failed) return ;
}
break;
case 20 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:124: T__86
{
mT__86(); if (state.failed) return ;
}
break;
case 21 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:130: T__87
{
mT__87(); if (state.failed) return ;
}
break;
case 22 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:136: T__88
{
mT__88(); if (state.failed) return ;
}
break;
case 23 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:142: T__89
{
mT__89(); if (state.failed) return ;
}
break;
case 24 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:148: T__90
{
mT__90(); if (state.failed) return ;
}
break;
case 25 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:154: T__91
{
mT__91(); if (state.failed) return ;
}
break;
case 26 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:160: T__92
{
mT__92(); if (state.failed) return ;
}
break;
case 27 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:166: T__93
{
mT__93(); if (state.failed) return ;
}
break;
case 28 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:172: T__94
{
mT__94(); if (state.failed) return ;
}
break;
case 29 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:178: T__95
{
mT__95(); if (state.failed) return ;
}
break;
case 30 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:184: T__96
{
mT__96(); if (state.failed) return ;
}
break;
case 31 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:190: T__97
{
mT__97(); if (state.failed) return ;
}
break;
case 32 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:196: T__98
{
mT__98(); if (state.failed) return ;
}
break;
case 33 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:202: T__99
{
mT__99(); if (state.failed) return ;
}
break;
case 34 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:208: T__100
{
mT__100(); if (state.failed) return ;
}
break;
case 35 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:215: T__101
{
mT__101(); if (state.failed) return ;
}
break;
case 36 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:222: T__102
{
mT__102(); if (state.failed) return ;
}
break;
case 37 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:229: T__103
{
mT__103(); if (state.failed) return ;
}
break;
case 38 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:236: T__104
{
mT__104(); if (state.failed) return ;
}
break;
case 39 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:243: T__105
{
mT__105(); if (state.failed) return ;
}
break;
case 40 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:250: T__106
{
mT__106(); if (state.failed) return ;
}
break;
case 41 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:257: T__107
{
mT__107(); if (state.failed) return ;
}
break;
case 42 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:264: T__108
{
mT__108(); if (state.failed) return ;
}
break;
case 43 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:271: T__109
{
mT__109(); if (state.failed) return ;
}
break;
case 44 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:278: T__110
{
mT__110(); if (state.failed) return ;
}
break;
case 45 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:285: T__111
{
mT__111(); if (state.failed) return ;
}
break;
case 46 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:292: T__112
{
mT__112(); if (state.failed) return ;
}
break;
case 47 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:299: T__113
{
mT__113(); if (state.failed) return ;
}
break;
case 48 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:306: T__114
{
mT__114(); if (state.failed) return ;
}
break;
case 49 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:313: T__115
{
mT__115(); if (state.failed) return ;
}
break;
case 50 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:320: T__116
{
mT__116(); if (state.failed) return ;
}
break;
case 51 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:327: T__117
{
mT__117(); if (state.failed) return ;
}
break;
case 52 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:334: T__118
{
mT__118(); if (state.failed) return ;
}
break;
case 53 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:341: T__119
{
mT__119(); if (state.failed) return ;
}
break;
case 54 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:348: T__120
{
mT__120(); if (state.failed) return ;
}
break;
case 55 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:355: T__121
{
mT__121(); if (state.failed) return ;
}
break;
case 56 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:362: T__122
{
mT__122(); if (state.failed) return ;
}
break;
case 57 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:369: T__123
{
mT__123(); if (state.failed) return ;
}
break;
case 58 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:376: T__124
{
mT__124(); if (state.failed) return ;
}
break;
case 59 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:383: T__125
{
mT__125(); if (state.failed) return ;
}
break;
case 60 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:390: T__126
{
mT__126(); if (state.failed) return ;
}
break;
case 61 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:397: T__127
{
mT__127(); if (state.failed) return ;
}
break;
case 62 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:404: T__128
{
mT__128(); if (state.failed) return ;
}
break;
case 63 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:411: T__129
{
mT__129(); if (state.failed) return ;
}
break;
case 64 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:418: T__130
{
mT__130(); if (state.failed) return ;
}
break;
case 65 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:425: T__131
{
mT__131(); if (state.failed) return ;
}
break;
case 66 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:432: T__132
{
mT__132(); if (state.failed) return ;
}
break;
case 67 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:439: T__133
{
mT__133(); if (state.failed) return ;
}
break;
case 68 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:446: T__134
{
mT__134(); if (state.failed) return ;
}
break;
case 69 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:453: T__135
{
mT__135(); if (state.failed) return ;
}
break;
case 70 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:460: T__136
{
mT__136(); if (state.failed) return ;
}
break;
case 71 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:467: T__137
{
mT__137(); if (state.failed) return ;
}
break;
case 72 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:474: T__138
{
mT__138(); if (state.failed) return ;
}
break;
case 73 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:481: T__139
{
mT__139(); if (state.failed) return ;
}
break;
case 74 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:488: T__140
{
mT__140(); if (state.failed) return ;
}
break;
case 75 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:495: T__141
{
mT__141(); if (state.failed) return ;
}
break;
case 76 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:502: T__142
{
mT__142(); if (state.failed) return ;
}
break;
case 77 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:509: T__143
{
mT__143(); if (state.failed) return ;
}
break;
case 78 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:516: T__144
{
mT__144(); if (state.failed) return ;
}
break;
case 79 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:523: T__145
{
mT__145(); if (state.failed) return ;
}
break;
case 80 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:530: T__146
{
mT__146(); if (state.failed) return ;
}
break;
case 81 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:537: T__147
{
mT__147(); if (state.failed) return ;
}
break;
case 82 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:544: T__148
{
mT__148(); if (state.failed) return ;
}
break;
case 83 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:551: T__149
{
mT__149(); if (state.failed) return ;
}
break;
case 84 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:558: T__150
{
mT__150(); if (state.failed) return ;
}
break;
case 85 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:565: T__151
{
mT__151(); if (state.failed) return ;
}
break;
case 86 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:572: T__152
{
mT__152(); if (state.failed) return ;
}
break;
case 87 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:579: T__153
{
mT__153(); if (state.failed) return ;
}
break;
case 88 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:586: T__154
{
mT__154(); if (state.failed) return ;
}
break;
case 89 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:593: T__155
{
mT__155(); if (state.failed) return ;
}
break;
case 90 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:600: T__156
{
mT__156(); if (state.failed) return ;
}
break;
case 91 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:607: T__157
{
mT__157(); if (state.failed) return ;
}
break;
case 92 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:614: T__158
{
mT__158(); if (state.failed) return ;
}
break;
case 93 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:621: T__159
{
mT__159(); if (state.failed) return ;
}
break;
case 94 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:628: T__160
{
mT__160(); if (state.failed) return ;
}
break;
case 95 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:635: T__161
{
mT__161(); if (state.failed) return ;
}
break;
case 96 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:642: T__162
{
mT__162(); if (state.failed) return ;
}
break;
case 97 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:649: T__163
{
mT__163(); if (state.failed) return ;
}
break;
case 98 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:656: T__164
{
mT__164(); if (state.failed) return ;
}
break;
case 99 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:663: T__165
{
mT__165(); if (state.failed) return ;
}
break;
case 100 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:670: T__166
{
mT__166(); if (state.failed) return ;
}
break;
case 101 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:677: T__167
{
mT__167(); if (state.failed) return ;
}
break;
case 102 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:684: T__168
{
mT__168(); if (state.failed) return ;
}
break;
case 103 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:691: T__169
{
mT__169(); if (state.failed) return ;
}
break;
case 104 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:698: T__170
{
mT__170(); if (state.failed) return ;
}
break;
case 105 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:705: T__171
{
mT__171(); if (state.failed) return ;
}
break;
case 106 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:712: T__172
{
mT__172(); if (state.failed) return ;
}
break;
case 107 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:719: T__173
{
mT__173(); if (state.failed) return ;
}
break;
case 108 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:726: T__174
{
mT__174(); if (state.failed) return ;
}
break;
case 109 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:733: T__175
{
mT__175(); if (state.failed) return ;
}
break;
case 110 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:740: T__176
{
mT__176(); if (state.failed) return ;
}
break;
case 111 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:747: T__177
{
mT__177(); if (state.failed) return ;
}
break;
case 112 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:754: T__178
{
mT__178(); if (state.failed) return ;
}
break;
case 113 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:761: T__179
{
mT__179(); if (state.failed) return ;
}
break;
case 114 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:768: KW_ASSIGN
{
mKW_ASSIGN(); if (state.failed) return ;
}
break;
case 115 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:778: KW_TRIREG
{
mKW_TRIREG(); if (state.failed) return ;
}
break;
case 116 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:788: AT
{
mAT(); if (state.failed) return ;
}
break;
case 117 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:791: COLON
{
mCOLON(); if (state.failed) return ;
}
break;
case 118 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:797: COMMA
{
mCOMMA(); if (state.failed) return ;
}
break;
case 119 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:803: DOT
{
mDOT(); if (state.failed) return ;
}
break;
case 120 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:807: ASSIGN
{
mASSIGN(); if (state.failed) return ;
}
break;
case 121 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:814: MINUS
{
mMINUS(); if (state.failed) return ;
}
break;
case 122 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:820: LBRACK
{
mLBRACK(); if (state.failed) return ;
}
break;
case 123 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:827: RBRACK
{
mRBRACK(); if (state.failed) return ;
}
break;
case 124 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:834: LCURLY
{
mLCURLY(); if (state.failed) return ;
}
break;
case 125 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:841: RCURLY
{
mRCURLY(); if (state.failed) return ;
}
break;
case 126 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:848: LPAREN
{
mLPAREN(); if (state.failed) return ;
}
break;
case 127 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:855: RPAREN
{
mRPAREN(); if (state.failed) return ;
}
break;
case 128 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:862: POUND
{
mPOUND(); if (state.failed) return ;
}
break;
case 129 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:868: QUESTION
{
mQUESTION(); if (state.failed) return ;
}
break;
case 130 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:877: SEMI
{
mSEMI(); if (state.failed) return ;
}
break;
case 131 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:882: PLUS
{
mPLUS(); if (state.failed) return ;
}
break;
case 132 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:887: LNOT
{
mLNOT(); if (state.failed) return ;
}
break;
case 133 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:892: BNOT
{
mBNOT(); if (state.failed) return ;
}
break;
case 134 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:897: BAND
{
mBAND(); if (state.failed) return ;
}
break;
case 135 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:902: RNAND
{
mRNAND(); if (state.failed) return ;
}
break;
case 136 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:908: BOR
{
mBOR(); if (state.failed) return ;
}
break;
case 137 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:912: RNOR
{
mRNOR(); if (state.failed) return ;
}
break;
case 138 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:917: BXOR
{
mBXOR(); if (state.failed) return ;
}
break;
case 139 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:922: BXNOR
{
mBXNOR(); if (state.failed) return ;
}
break;
case 140 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:928: STAR
{
mSTAR(); if (state.failed) return ;
}
break;
case 141 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:933: DIV
{
mDIV(); if (state.failed) return ;
}
break;
case 142 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:937: MOD
{
mMOD(); if (state.failed) return ;
}
break;
case 143 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:941: EQUAL
{
mEQUAL(); if (state.failed) return ;
}
break;
case 144 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:947: NOT_EQ
{
mNOT_EQ(); if (state.failed) return ;
}
break;
case 145 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:954: NOT_EQ_CASE
{
mNOT_EQ_CASE(); if (state.failed) return ;
}
break;
case 146 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:966: EQ_CASE
{
mEQ_CASE(); if (state.failed) return ;
}
break;
case 147 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:974: LAND
{
mLAND(); if (state.failed) return ;
}
break;
case 148 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:979: LOR
{
mLOR(); if (state.failed) return ;
}
break;
case 149 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:983: LT_
{
mLT_(); if (state.failed) return ;
}
break;
case 150 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:987: LE
{
mLE(); if (state.failed) return ;
}
break;
case 151 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:990: GT
{
mGT(); if (state.failed) return ;
}
break;
case 152 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:993: GE
{
mGE(); if (state.failed) return ;
}
break;
case 153 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:996: SR
{
mSR(); if (state.failed) return ;
}
break;
case 154 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:999: SL
{
mSL(); if (state.failed) return ;
}
break;
case 155 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1002: TRIGGER
{
mTRIGGER(); if (state.failed) return ;
}
break;
case 156 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1010: PPATH
{
mPPATH(); if (state.failed) return ;
}
break;
case 157 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1016: FPATH
{
mFPATH(); if (state.failed) return ;
}
break;
case 158 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1022: IDENTIFIER
{
mIDENTIFIER(); if (state.failed) return ;
}
break;
case 159 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1033: ESCAPED_IDENTIFIER
{
mESCAPED_IDENTIFIER(); if (state.failed) return ;
}
break;
case 160 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1052: SYSTEM_TASK_NAME
{
mSYSTEM_TASK_NAME(); if (state.failed) return ;
}
break;
case 161 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1069: STRING
{
mSTRING(); if (state.failed) return ;
}
break;
case 162 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1076: DEFINE
{
mDEFINE(); if (state.failed) return ;
}
break;
case 163 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1083: NUMBER
{
mNUMBER(); if (state.failed) return ;
}
break;
case 164 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1090: WS
{
mWS(); if (state.failed) return ;
}
break;
case 165 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1093: ML_COMMENT
{
mML_COMMENT(); if (state.failed) return ;
}
break;
case 166 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1:1104: SL_COMMENT
{
mSL_COMMENT(); if (state.failed) return ;
}
break;
}
}
// $ANTLR start synpred1_Verilog
public final void synpred1_Verilog_fragment() throws RecognitionException {
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1108:2: ( ( SIZE )? BASE SIZED_DIGIT )
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1108:4: ( SIZE )? BASE SIZED_DIGIT
{
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1108:4: ( SIZE )?
int alt22=2;
int LA22_0 = input.LA(1);
if ( ((LA22_0>='0' && LA22_0<='9')) ) {
alt22=1;
}
switch (alt22) {
case 1 :
// C:\\Users\\rozagh\\Documents\\NetBeansProjects\\VerilogParser2\\Verilog.g:1108:5: SIZE
{
mSIZE(); if (state.failed) return ;
}
break;
}
mBASE(); if (state.failed) return ;
mSIZED_DIGIT(); if (state.failed) return ;
}
}
// $ANTLR end synpred1_Verilog
public final boolean synpred1_Verilog() {
state.backtracking++;
int start = input.mark();
try {
synpred1_Verilog_fragment(); // can never throw exception
} catch (RecognitionException re) {
System.err.println("impossible: "+re);
}
boolean success = !state.failed;
input.rewind(start);
state.backtracking--;
state.failed=false;
return success;
}
protected DFA5 dfa5 = new DFA5(this);
protected DFA21 dfa21 = new DFA21(this);
static final String DFA5_eotS =
"\1\uffff\1\3\2\uffff\1\3";
static final String DFA5_eofS =
"\5\uffff";
static final String DFA5_minS =
"\2\47\2\uffff\1\47";
static final String DFA5_maxS =
"\2\71\2\uffff\1\71";
static final String DFA5_acceptS =
"\2\uffff\1\1\1\2\1\uffff";
static final String DFA5_specialS =
"\1\2\1\0\2\uffff\1\1}>";
static final String[] DFA5_transitionS = {
"\1\2\10\uffff\12\1",
"\1\2\10\uffff\12\4",
"",
"",
"\1\2\10\uffff\12\4"
};
static final short[] DFA5_eot = DFA.unpackEncodedString(DFA5_eotS);
static final short[] DFA5_eof = DFA.unpackEncodedString(DFA5_eofS);
static final char[] DFA5_min = DFA.unpackEncodedStringToUnsignedChars(DFA5_minS);
static final char[] DFA5_max = DFA.unpackEncodedStringToUnsignedChars(DFA5_maxS);
static final short[] DFA5_accept = DFA.unpackEncodedString(DFA5_acceptS);
static final short[] DFA5_special = DFA.unpackEncodedString(DFA5_specialS);
static final short[][] DFA5_transition;
static {
int numStates = DFA5_transitionS.length;
DFA5_transition = new short[numStates][];
for (int i=0; i<numStates; i++) {
DFA5_transition[i] = DFA.unpackEncodedString(DFA5_transitionS[i]);
}
}
class DFA5 extends DFA {
public DFA5(BaseRecognizer recognizer) {
this.recognizer = recognizer;
this.decisionNumber = 5;
this.eot = DFA5_eot;
this.eof = DFA5_eof;
this.min = DFA5_min;
this.max = DFA5_max;
this.accept = DFA5_accept;
this.special = DFA5_special;
this.transition = DFA5_transition;
}
public String getDescription() {
return "1107:1: NUMBER : ( ( ( SIZE )? BASE SIZED_DIGIT )=> SIZED_NUMBER | UNSIZED_NUMBER );";
}
public int specialStateTransition(int s, IntStream _input) throws NoViableAltException {
IntStream input = _input;
int _s = s;
switch ( s ) {
case 0 :
int LA5_1 = input.LA(1);
int index5_1 = input.index();
input.rewind();
s = -1;
if ( (LA5_1=='\'') && (synpred1_Verilog())) {s = 2;}
else if ( ((LA5_1>='0' && LA5_1<='9')) ) {s = 4;}
else s = 3;
input.seek(index5_1);
if ( s>=0 ) return s;
break;
case 1 :
int LA5_4 = input.LA(1);
int index5_4 = input.index();
input.rewind();
s = -1;
if ( (LA5_4=='\'') && (synpred1_Verilog())) {s = 2;}
else if ( ((LA5_4>='0' && LA5_4<='9')) ) {s = 4;}
else s = 3;
input.seek(index5_4);
if ( s>=0 ) return s;
break;
case 2 :
int LA5_0 = input.LA(1);
int index5_0 = input.index();
input.rewind();
s = -1;
if ( ((LA5_0>='0' && LA5_0<='9')) ) {s = 1;}
else if ( (LA5_0=='\'') && (synpred1_Verilog())) {s = 2;}
input.seek(index5_0);
if ( s>=0 ) return s;
break;
}
if (state.backtracking>0) {state.failed=true; return -1;}
NoViableAltException nvae =
new NoViableAltException(getDescription(), 5, _s, input);
error(nvae);
throw nvae;
}
}
static final String DFA21_eotS =
"\1\uffff\4\63\1\66\20\63\1\uffff\1\170\1\66\5\uffff\1\177\1\u0081"+
"\12\uffff\1\u0083\1\u0087\1\u0089\1\u008a\1\u008c\1\u008f\1\uffff"+
"\1\u0092\1\u0095\5\uffff\15\63\1\u00a6\2\uffff\13\63\1\u00b8\35"+
"\63\5\166\1\uffff\1\u00e0\2\uffff\2\174\1\uffff\1\u00e4\4\uffff"+
"\1\u00e6\23\uffff\3\63\1\u00f0\14\63\2\uffff\2\63\1\u0107\3\63\1"+
"\u010e\1\63\1\u0110\7\63\1\uffff\3\63\1\u011b\15\63\1\u012a\3\63"+
"\1\u012e\1\u0130\2\63\1\u0133\1\63\1\u0136\4\63\6\166\2\uffff\2"+
"\174\4\uffff\11\63\1\uffff\1\63\1\u014d\1\u014e\3\63\1\u0155\5\63"+
"\1\u015b\1\u015c\1\u015d\1\63\1\u015f\1\u0160\1\63\1\u0162\2\63"+
"\1\uffff\1\u0166\1\u0167\2\63\1\u016a\1\63\1\uffff\1\u016c\1\uffff"+
"\7\63\1\u0174\1\u0175\1\u0176\1\uffff\16\63\1\uffff\2\63\1\u0189"+
"\1\uffff\1\63\1\uffff\1\u018b\1\63\1\uffff\1\u018d\1\63\1\uffff"+
"\1\63\1\u0190\1\u0193\1\u0194\6\166\2\174\11\63\1\u01a7\2\uffff"+
"\2\63\1\u01aa\1\u01ab\2\63\1\uffff\3\63\1\u01b1\1\u01b2\3\uffff"+
"\1\u01b3\2\uffff\1\63\1\uffff\1\u01b5\2\63\2\uffff\2\63\1\uffff"+
"\1\u01ba\1\uffff\2\63\1\u01bd\1\u01be\1\u01bf\1\u01c1\1\63\3\uffff"+
"\1\u01c3\1\u01c4\1\u01c5\2\63\1\u01c8\10\63\1\u01d1\3\63\1\uffff"+
"\1\63\1\uffff\1\63\1\uffff\1\63\1\u01db\1\uffff\1\u01dc\1\u01dd"+
"\2\uffff\1\166\1\u01df\1\u01e0\3\166\2\174\1\u01e6\1\63\1\u01e8"+
"\7\63\1\uffff\2\63\2\uffff\1\63\1\u01f3\3\63\3\uffff\1\u01f7\1\uffff"+
"\1\u01f8\3\63\1\uffff\1\u01fd\1\63\3\uffff\1\63\1\uffff\1\u0200"+
"\3\uffff\2\63\1\uffff\10\63\1\uffff\1\u020d\1\u020e\1\u020f\1\u0210"+
"\1\u0211\1\u0212\1\63\1\u0214\1\u0215\3\uffff\1\u0217\2\uffff\1"+
"\166\1\u0219\1\166\2\174\1\uffff\1\63\1\uffff\3\63\1\u0221\1\63"+
"\1\u0223\4\63\1\uffff\1\u0228\1\u0229\1\u022a\2\uffff\1\u022b\1"+
"\u022c\1\63\1\u022e\1\uffff\1\u022f\1\63\1\uffff\1\u0232\1\u0233"+
"\1\63\1\u0235\1\u0236\1\u0237\3\63\1\u023b\1\63\1\u023d\6\uffff"+
"\1\u023e\2\uffff\1\166\1\uffff\1\u0240\1\uffff\1\166\1\u0242\1\174"+
"\3\63\1\u0247\1\uffff\1\63\1\uffff\3\63\1\u024c\5\uffff\1\u024d"+
"\2\uffff\1\u024e\1\u024f\2\uffff\1\u0250\3\uffff\1\63\1\u0252\1"+
"\u0253\1\uffff\1\u0254\2\uffff\1\166\1\uffff\1\166\1\uffff\1\u0257"+
"\1\63\1\u0259\1\63\1\uffff\2\63\1\u025d\1\u025e\5\uffff\1\u025f"+
"\3\uffff\1\166\1\u0261\1\uffff\1\63\1\uffff\2\63\1\u0265\3\uffff"+
"\1\u0266\1\uffff\1\u0267\1\63\1\u0269\3\uffff\1\u026a\2\uffff";
static final String DFA21_eofS =
"\u026b\uffff";
static final String DFA21_minS =
"\1\11\1\141\1\144\1\141\1\146\1\47\1\141\1\157\1\143\1\162\1\141"+
"\1\143\2\145\1\141\1\151\1\154\1\141\1\156\1\145\1\141\1\157\1\101"+
"\1\46\1\170\1\101\4\uffff\1\75\1\76\12\uffff\1\75\1\46\1\174\1\176"+
"\1\76\1\52\1\uffff\1\74\1\75\5\uffff\1\144\1\143\2\144\1\145\1\163"+
"\1\147\1\151\1\162\1\154\1\157\1\163\1\151\1\44\1\102\1\uffff\1"+
"\142\1\141\1\155\1\156\1\162\1\141\3\155\1\162\1\164\1\44\1\162"+
"\1\151\1\162\1\141\1\151\1\160\2\141\1\162\1\145\1\143\1\141\1\163"+
"\1\162\1\147\1\144\1\167\1\163\1\156\1\162\1\157\1\147\1\162\1\157"+
"\1\146\1\147\1\157\1\163\1\151\1\145\1\157\1\145\1\151\1\145\1\uffff"+
"\1\46\2\uffff\1\145\1\156\1\uffff\1\75\4\uffff\1\75\23\uffff\1\165"+
"\1\162\1\151\1\44\1\156\2\145\1\155\1\141\1\154\1\163\1\145\1\164"+
"\1\145\2\165\1\uffff\1\60\1\154\1\153\1\44\1\156\1\145\1\143\1\44"+
"\1\154\1\44\2\145\3\157\1\141\1\160\1\uffff\1\145\1\144\1\164\1"+
"\44\1\153\1\154\1\160\2\154\1\157\1\143\1\164\1\141\1\163\1\141"+
"\1\147\1\150\1\44\1\141\1\151\1\144\2\44\1\163\1\145\1\44\1\162"+
"\1\44\1\151\1\163\1\145\1\156\1\164\1\145\1\154\1\162\1\144\1\143"+
"\2\uffff\1\146\1\143\4\uffff\1\154\1\157\1\165\1\157\1\162\1\141"+
"\1\165\1\141\1\160\1\uffff\1\164\2\44\1\151\1\155\1\60\1\44\1\144"+
"\1\151\1\147\2\164\3\60\1\145\2\44\1\156\1\44\1\162\1\145\1\uffff"+
"\2\44\1\164\1\166\1\44\1\145\1\uffff\1\44\1\uffff\2\141\3\163\1"+
"\156\1\165\3\44\1\uffff\1\60\1\145\1\154\1\141\1\154\1\156\1\151"+
"\1\157\1\141\1\165\1\163\1\142\1\145\1\172\1\uffff\1\171\1\147\1"+
"\44\1\uffff\1\146\1\uffff\1\44\1\144\1\uffff\1\44\1\146\1\uffff"+
"\1\156\3\44\1\165\1\167\1\144\1\151\1\164\1\157\1\151\1\154\1\145"+
"\2\155\1\144\1\151\1\142\1\156\1\163\1\145\1\44\2\uffff\1\164\1"+
"\145\2\44\1\157\1\160\1\uffff\1\147\1\141\1\145\2\44\3\uffff\1\44"+
"\2\uffff\1\144\1\uffff\1\44\1\147\1\146\2\uffff\1\151\1\145\1\uffff"+
"\1\44\1\uffff\1\164\1\163\4\44\1\164\3\uffff\3\44\1\171\1\162\1"+
"\44\1\147\1\146\1\141\2\162\1\154\1\151\1\154\1\44\1\60\1\163\1"+
"\156\1\uffff\1\60\1\uffff\1\147\1\uffff\1\60\1\44\1\uffff\2\44\2"+
"\uffff\1\160\2\44\1\157\1\150\1\166\1\156\1\165\1\44\1\157\1\44"+
"\1\165\1\155\1\154\1\153\1\143\1\145\1\143\1\uffff\1\151\1\164\2"+
"\uffff\1\167\1\44\1\145\1\154\1\162\3\uffff\1\44\1\uffff\1\44\1"+
"\60\1\157\1\162\1\uffff\1\44\1\145\3\uffff\1\146\1\uffff\1\44\3"+
"\uffff\1\60\1\145\1\uffff\1\60\1\171\1\162\1\145\1\141\1\164\1\147"+
"\1\145\1\uffff\6\44\1\145\2\44\3\uffff\1\44\2\uffff\1\144\1\44\2"+
"\145\1\144\1\uffff\1\144\1\uffff\1\154\1\151\1\145\1\44\1\164\1"+
"\44\1\151\1\166\1\145\1\156\1\uffff\3\44\2\uffff\2\44\1\156\1\44"+
"\1\uffff\1\44\1\60\1\uffff\2\44\1\144\3\44\1\141\1\144\1\155\1\44"+
"\1\156\1\44\6\uffff\1\44\2\uffff\1\157\1\uffff\1\44\1\uffff\1\162"+
"\1\44\1\145\1\165\1\145\1\164\1\44\1\uffff\1\151\1\uffff\1\146\1"+
"\145\1\162\1\44\5\uffff\1\44\2\uffff\2\44\2\uffff\1\44\3\uffff\1"+
"\155\2\44\1\uffff\1\44\2\uffff\1\154\1\uffff\1\171\1\uffff\1\44"+
"\1\154\1\44\1\151\1\uffff\1\157\1\171\2\44\5\uffff\1\44\3\uffff"+
"\1\144\1\44\1\uffff\1\145\1\uffff\1\166\1\156\1\44\3\uffff\1\44"+
"\1\uffff\1\44\1\145\1\44\3\uffff\1\44\2\uffff";
static final String DFA21_maxS =
"\1\176\1\157\1\166\1\165\1\156\1\170\1\162\1\165\1\164\1\165\1"+
"\157\1\165\1\145\1\151\1\141\1\151\1\163\2\157\1\165\1\155\1\157"+
"\1\172\1\46\1\170\1\172\4\uffff\2\76\12\uffff\1\75\2\174\1\176\1"+
"\76\1\57\1\uffff\1\75\1\76\5\uffff\1\144\1\143\2\144\1\145\1\163"+
"\1\147\1\151\1\162\1\154\1\157\1\163\1\164\1\172\1\157\1\uffff\1"+
"\163\1\151\1\155\1\156\1\162\1\160\3\155\1\162\1\164\1\172\1\162"+
"\1\156\1\162\1\141\1\151\1\160\2\141\1\162\1\145\1\143\1\146\1\163"+
"\1\162\1\147\1\144\1\167\1\163\1\156\1\164\1\157\1\147\1\162\1\157"+
"\1\146\1\147\1\157\1\163\1\151\1\153\1\157\1\145\1\151\1\145\1\uffff"+
"\1\46\2\uffff\1\145\1\156\1\uffff\1\75\4\uffff\1\75\23\uffff\1\165"+
"\1\162\1\151\1\172\1\156\2\145\1\155\1\141\1\154\1\163\1\145\1\164"+
"\1\145\2\165\1\uffff\1\172\1\154\1\153\1\172\1\156\1\145\1\143\1"+
"\172\1\154\1\172\2\145\3\157\1\141\1\160\1\uffff\1\145\1\144\1\164"+
"\1\172\1\153\1\154\1\160\2\154\1\157\1\143\1\164\1\160\1\163\1\141"+
"\1\147\1\150\1\172\1\141\1\151\1\144\2\172\1\163\1\145\1\172\1\162"+
"\1\172\1\151\1\163\1\145\1\156\1\164\1\145\1\154\1\162\1\144\1\143"+
"\2\uffff\1\146\1\143\4\uffff\1\154\1\157\1\165\1\157\1\162\1\141"+
"\1\165\1\141\1\160\1\uffff\1\164\2\172\1\151\1\155\1\165\1\172\1"+
"\144\1\151\1\147\2\164\3\172\1\145\2\172\1\156\1\172\1\162\1\145"+
"\1\uffff\2\172\1\164\1\166\1\172\1\145\1\uffff\1\172\1\uffff\2\141"+
"\3\163\1\156\1\165\3\172\1\uffff\1\61\1\145\1\154\1\141\1\154\1"+
"\156\1\160\1\157\1\141\1\165\1\163\1\142\1\145\1\172\1\uffff\1\171"+
"\1\147\1\172\1\uffff\1\146\1\uffff\1\172\1\144\1\uffff\1\172\1\146"+
"\1\uffff\1\156\3\172\1\165\1\167\1\144\1\151\1\164\1\157\1\151\1"+
"\154\1\145\2\155\1\144\1\151\1\163\1\156\1\163\1\145\1\172\2\uffff"+
"\1\164\1\145\2\172\1\157\1\160\1\uffff\1\147\1\141\1\145\2\172\3"+
"\uffff\1\172\2\uffff\1\144\1\uffff\1\172\1\147\1\146\2\uffff\1\151"+
"\1\145\1\uffff\1\172\1\uffff\1\164\1\163\4\172\1\164\3\uffff\3\172"+
"\1\171\1\162\1\172\1\147\1\146\1\141\2\162\1\154\1\151\1\154\1\172"+
"\1\61\1\163\1\156\1\uffff\1\61\1\uffff\1\147\1\uffff\1\61\1\172"+
"\1\uffff\2\172\2\uffff\1\160\2\172\1\157\1\150\1\166\1\156\1\165"+
"\1\172\1\157\1\172\1\165\1\155\1\154\1\153\1\143\1\145\1\143\1\uffff"+
"\1\151\1\164\2\uffff\1\167\1\172\1\145\1\154\1\162\3\uffff\1\172"+
"\1\uffff\1\172\1\61\1\157\1\162\1\uffff\1\172\1\145\3\uffff\1\146"+
"\1\uffff\1\172\3\uffff\1\61\1\145\1\uffff\1\61\1\171\1\162\1\145"+
"\1\141\1\164\1\147\1\145\1\uffff\6\172\1\145\2\172\3\uffff\1\172"+
"\2\uffff\1\144\1\172\2\145\1\144\1\uffff\1\144\1\uffff\1\154\1\151"+
"\1\145\1\172\1\164\1\172\1\151\1\166\1\145\1\156\1\uffff\3\172\2"+
"\uffff\2\172\1\156\1\172\1\uffff\1\172\1\61\1\uffff\2\172\1\144"+
"\3\172\1\141\1\144\1\155\1\172\1\156\1\172\6\uffff\1\172\2\uffff"+
"\1\157\1\uffff\1\172\1\uffff\1\162\1\172\1\145\1\165\1\145\1\164"+
"\1\172\1\uffff\1\151\1\uffff\1\146\1\145\1\162\1\172\5\uffff\1\172"+
"\2\uffff\2\172\2\uffff\1\172\3\uffff\1\155\2\172\1\uffff\1\172\2"+
"\uffff\1\154\1\uffff\1\171\1\uffff\1\172\1\154\1\172\1\151\1\uffff"+
"\1\157\1\171\2\172\5\uffff\1\172\3\uffff\1\144\1\172\1\uffff\1\145"+
"\1\uffff\1\166\1\156\1\172\3\uffff\1\172\1\uffff\1\172\1\145\1\172"+
"\3\uffff\1\172\2\uffff";
static final String DFA21_acceptS =
"\32\uffff\1\164\1\165\1\166\1\167\2\uffff\1\172\1\173\1\174\1\175"+
"\1\176\1\177\1\u0080\1\u0081\1\u0082\1\u0083\6\uffff\1\u008e\2\uffff"+
"\1\u009e\1\u009f\1\u00a1\1\u00a3\1\u00a4\17\uffff\1\157\56\uffff"+
"\1\u00a0\1\uffff\1\u0086\1\156\2\uffff\1\u00a2\1\uffff\1\u009c\1"+
"\170\1\u009b\1\171\1\uffff\1\u0084\1\u0087\1\u0089\1\u008b\1\u0085"+
"\1\u0094\1\u0088\1\u008a\1\u009d\1\u008c\1\u00a5\1\u00a6\1\u008d"+
"\1\u0096\1\u009a\1\u0095\1\u0098\1\u0099\1\u0097\20\uffff\1\114"+
"\21\uffff\1\63\46\uffff\1\152\1\u0093\2\uffff\1\u0092\1\u008f\1"+
"\u0091\1\u0090\11\uffff\1\132\26\uffff\1\27\6\uffff\1\126\1\uffff"+
"\1\42\12\uffff\1\36\16\uffff\1\61\3\uffff\1\64\1\uffff\1\72\2\uffff"+
"\1\65\2\uffff\1\67\26\uffff\1\115\1\155\6\uffff\1\101\5\uffff\1"+
"\7\1\10\1\11\1\uffff\1\14\1\30\1\uffff\1\34\3\uffff\1\105\1\43\2"+
"\uffff\1\133\1\uffff\1\21\7\uffff\1\26\1\32\1\127\22\uffff\1\62"+
"\1\uffff\1\77\1\uffff\1\66\2\uffff\1\103\2\uffff\1\117\1\134\22"+
"\uffff\1\44\2\uffff\1\52\1\56\5\uffff\1\23\1\25\1\12\1\uffff\1\37"+
"\4\uffff\1\136\2\uffff\1\100\1\102\1\104\1\uffff\1\106\1\uffff\1"+
"\53\1\57\1\125\2\uffff\1\46\10\uffff\1\50\11\uffff\1\131\1\120\1"+
"\121\1\uffff\1\147\1\144\5\uffff\1\1\1\uffff\1\47\12\uffff\1\76"+
"\3\uffff\1\33\1\163\4\uffff\1\124\2\uffff\1\24\14\uffff\1\54\1\60"+
"\1\113\1\162\1\73\1\74\1\uffff\1\70\1\71\1\uffff\1\143\1\uffff\1"+
"\146\7\uffff\1\15\1\uffff\1\116\4\uffff\1\153\1\6\1\20\1\107\1\111"+
"\1\uffff\1\123\1\137\2\uffff\1\31\1\35\1\uffff\1\51\1\55\1\140\3"+
"\uffff\1\122\1\uffff\1\130\1\154\1\uffff\1\145\1\uffff\1\160\4\uffff"+
"\1\13\4\uffff\1\75\1\16\1\110\1\112\1\40\1\uffff\1\41\1\45\1\135"+
"\2\uffff\1\161\1\uffff\1\3\3\uffff\1\4\1\22\1\142\1\uffff\1\150"+
"\3\uffff\1\141\1\151\1\2\1\uffff\1\17\1\5";
static final String DFA21_specialS =
"\u026b\uffff}>";
static final String[] DFA21_transitionS = {
"\1\67\26\uffff\1\67\1\52\1\65\1\46\1\26\1\60\1\27\1\66\1\44"+
"\1\45\1\56\1\51\1\34\1\37\1\35\1\57\1\30\1\5\10\66\1\33\1\50"+
"\1\61\1\36\1\62\1\47\1\32\32\63\1\40\1\64\1\41\1\55\1\63\1\31"+
"\1\20\1\23\1\24\1\15\1\2\1\7\1\63\1\17\1\4\1\25\1\63\1\16\1"+
"\1\1\21\1\11\1\3\1\63\1\10\1\13\1\6\1\63\1\14\1\12\1\22\2\63"+
"\1\42\1\54\1\43\1\53",
"\1\71\3\uffff\1\72\11\uffff\1\70",
"\1\76\7\uffff\1\75\1\uffff\1\73\7\uffff\1\74",
"\1\100\13\uffff\1\102\1\uffff\1\103\2\uffff\1\77\2\uffff\1"+
"\101",
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"\1\106\120\uffff\1\107",
"\1\110\7\uffff\1\112\10\uffff\1\111",
"\1\114\5\uffff\1\113",
"\1\120\1\uffff\1\115\10\uffff\1\116\1\uffff\1\117\3\uffff"+
"\1\121",
"\1\123\2\uffff\1\122",
"\1\125\3\uffff\1\127\2\uffff\1\130\1\124\5\uffff\1\126",
"\1\132\11\uffff\1\133\2\uffff\1\135\3\uffff\1\134\1\131",
"\1\136",
"\1\137\3\uffff\1\140",
"\1\141",
"\1\142",
"\1\144\1\uffff\1\143\4\uffff\1\145",
"\1\146\3\uffff\1\151\7\uffff\1\150\1\uffff\1\147",
"\1\153\1\152",
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"\1\165\1\161\3\166\1\164\3\166",
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"\32\174\4\uffff\1\174\1\uffff\3\174\1\172\4\174\1\173\21\174",
"",
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"\63",
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"\63",
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"\63\1\u012f\21\63",
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"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
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"\63\1\u0135\21\63",
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"\63",
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"\63",
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"\4\uffff\1\66\1\uffff\6\66\21\uffff\1\66\1\uffff\1\66",
"\12\66\5\uffff\1\66\1\uffff\6\66\21\uffff\1\66\1\uffff\1\66"+
"\4\uffff\1\66\1\uffff\6\66\21\uffff\1\66\1\uffff\1\66",
"\12\66\5\uffff\1\66\1\uffff\6\66\21\uffff\1\66\1\uffff\1\66"+
"\4\uffff\1\66\1\uffff\6\66\21\uffff\1\66\1\uffff\1\66",
"\1\u015e",
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"\63",
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"\63",
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"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
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"\63\1\u0165\21\63",
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"\63",
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"\63",
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"\63",
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"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
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"\63",
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"",
"",
"\1\u0218",
"\1\166\13\uffff\12\166\7\uffff\32\166\4\uffff\1\166\1\uffff"+
"\32\166",
"\1\u021a",
"\1\u021b",
"\1\u021c",
"",
"\1\u021d",
"",
"\1\u021e",
"\1\u021f",
"\1\u0220",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\u0222",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\u0224",
"\1\u0225",
"\1\u0226",
"\1\u0227",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\u022d",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\u0230\1\u0231",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\u0234",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\u0238",
"\1\u0239",
"\1\u023a",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\u023c",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"",
"",
"",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"\1\u023f",
"",
"\1\166\13\uffff\12\166\7\uffff\32\166\4\uffff\1\166\1\uffff"+
"\32\166",
"",
"\1\u0241",
"\1\174\13\uffff\12\174\7\uffff\32\174\4\uffff\1\174\1\uffff"+
"\32\174",
"\1\u0243",
"\1\u0244",
"\1\u0245",
"\1\u0246",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"\1\u0248",
"",
"\1\u0249",
"\1\u024a",
"\1\u024b",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"",
"",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"",
"\1\u0251",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"\1\u0255",
"",
"\1\u0256",
"",
"\1\174\13\uffff\12\174\7\uffff\32\174\4\uffff\1\174\1\uffff"+
"\32\174",
"\1\u0258",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\u025a",
"",
"\1\u025b",
"\1\u025c",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"",
"",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"",
"\1\u0260",
"\1\166\13\uffff\12\166\7\uffff\32\166\4\uffff\1\166\1\uffff"+
"\32\166",
"",
"\1\u0262",
"",
"\1\u0263",
"\1\u0264",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"",
"\1\166\13\uffff\12\166\7\uffff\32\166\4\uffff\1\166\1\uffff"+
"\32\166",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"\1\u0268",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
"",
"",
"\1\63\13\uffff\12\63\7\uffff\32\63\4\uffff\1\63\1\uffff\32"+
"\63",
"",
""
};
static final short[] DFA21_eot = DFA.unpackEncodedString(DFA21_eotS);
static final short[] DFA21_eof = DFA.unpackEncodedString(DFA21_eofS);
static final char[] DFA21_min = DFA.unpackEncodedStringToUnsignedChars(DFA21_minS);
static final char[] DFA21_max = DFA.unpackEncodedStringToUnsignedChars(DFA21_maxS);
static final short[] DFA21_accept = DFA.unpackEncodedString(DFA21_acceptS);
static final short[] DFA21_special = DFA.unpackEncodedString(DFA21_specialS);
static final short[][] DFA21_transition;
static {
int numStates = DFA21_transitionS.length;
DFA21_transition = new short[numStates][];
for (int i=0; i<numStates; i++) {
DFA21_transition[i] = DFA.unpackEncodedString(DFA21_transitionS[i]);
}
}
class DFA21 extends DFA {
public DFA21(BaseRecognizer recognizer) {
this.recognizer = recognizer;
this.decisionNumber = 21;
this.eot = DFA21_eot;
this.eof = DFA21_eof;
this.min = DFA21_min;
this.max = DFA21_max;
this.accept = DFA21_accept;
this.special = DFA21_special;
this.transition = DFA21_transition;
}
public String getDescription() {
return "1:1: Tokens : ( T__67 | T__68 | T__69 | T__70 | T__71 | T__72 | T__73 | T__74 | T__75 | T__76 | T__77 | T__78 | T__79 | T__80 | T__81 | T__82 | T__83 | T__84 | T__85 | T__86 | T__87 | T__88 | T__89 | T__90 | T__91 | T__92 | T__93 | T__94 | T__95 | T__96 | T__97 | T__98 | T__99 | T__100 | T__101 | T__102 | T__103 | T__104 | T__105 | T__106 | T__107 | T__108 | T__109 | T__110 | T__111 | T__112 | T__113 | T__114 | T__115 | T__116 | T__117 | T__118 | T__119 | T__120 | T__121 | T__122 | T__123 | T__124 | T__125 | T__126 | T__127 | T__128 | T__129 | T__130 | T__131 | T__132 | T__133 | T__134 | T__135 | T__136 | T__137 | T__138 | T__139 | T__140 | T__141 | T__142 | T__143 | T__144 | T__145 | T__146 | T__147 | T__148 | T__149 | T__150 | T__151 | T__152 | T__153 | T__154 | T__155 | T__156 | T__157 | T__158 | T__159 | T__160 | T__161 | T__162 | T__163 | T__164 | T__165 | T__166 | T__167 | T__168 | T__169 | T__170 | T__171 | T__172 | T__173 | T__174 | T__175 | T__176 | T__177 | T__178 | T__179 | KW_ASSIGN | KW_TRIREG | AT | COLON | COMMA | DOT | ASSIGN | MINUS | LBRACK | RBRACK | LCURLY | RCURLY | LPAREN | RPAREN | POUND | QUESTION | SEMI | PLUS | LNOT | BNOT | BAND | RNAND | BOR | RNOR | BXOR | BXNOR | STAR | DIV | MOD | EQUAL | NOT_EQ | NOT_EQ_CASE | EQ_CASE | LAND | LOR | LT_ | LE | GT | GE | SR | SL | TRIGGER | PPATH | FPATH | IDENTIFIER | ESCAPED_IDENTIFIER | SYSTEM_TASK_NAME | STRING | DEFINE | NUMBER | WS | ML_COMMENT | SL_COMMENT );";
}
}
}